MM74HCT74

更新时间： 2024-11-22 23:02:43

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
7页	88K
描述
Dual D-Type Flip-Flop with Preset and Clear

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中文翻译

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数据手册

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MM74HCT74 数据手册

February 1984

Revised January 1999

MM74HCT74

Dual D-Type Flip-Flop with Preset and Clear

tected from damage due to static discharge by internal

diode clamps to V_CCand ground.

General Description

The MM74HCT74 utilizes advanced silicon-gate CMOS

technology to achieve operation speeds similar to the

equivalent LS-TTL part. It possesses the high noise immu-

nity and low power consumption of standard CMOS inte-

grated circuits, along with the ability to drive 10 LS-TTL

loads.

MM74HCT devices are intended to interface between TTL

and NMOS components and standard CMOS devices.

These parts are also plug-in replacements for LS-TTL

devices and can be used to reduce power consumption in

existing designs.

This flip-flop has independent data, preset, clear, and clock

inputs and Q and Q outputs. The logic level present at the

data input is transferred to the output during the positive-

going transition of the clock pulse. Preset and clear are

independent of the clock and accomplished by a low level

at the appropriate input.

Features

■ Typical propagation delay: 20 ns

■ Low quiescent current: 40 µA maximum (74HCT Series)

■ Low input current: 1 µA maximum

■ Fanout of 10 LS-TTL loads

The 74HCT logic family is functionally and pin-out compati-

ble with the standard 74LS logic family. All inputs are pro-

■ Meta-stable hardened

Ordering Code:

Order Number Package Number

Package Description

MM74HCT74M

MM74HCT74SJ

M74HCT74MTC

MM74HCT74N

M14A

M14D

MTC14

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Pin Assignments for DIP, SOIC, SOP and TSSOP

Inputs

Outputs

CLR

CLK

(Note 1) (Note 1)

↑

Q0 = the level of Q before the indicated input conditions were established.

Note 1: This configuration is nonstable; that is, it will not persist when pre-

set and clear inputs return to their inactive (HIGH) level.

DS005360.prf

www.fairchildsemi.com

12 3 4 5 6 7

中文翻译

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与MM74HCT74相关器件

型号	品牌	获取价格	描述	数据表
MM74HCT74_05	FAIRCHILD	获取价格	Dual D-Type Flip-Flop with Preset and Clear
MM74HCT74_08	FAIRCHILD	获取价格	MM74HCT74 Dual D-Type Flip-Flop with Preset and Clear
MM74HCT74J/A+	ETC	获取价格	Dual D-Type Flip-Flop
MM74HCT74M	FAIRCHILD	获取价格	Dual D-Type Flip-Flop with Preset and Clear
MM74HCT74M	ONSEMI	获取价格	双路 D 类触发器，带预设和清除输入
MM74HCT74M/A+	ETC	获取价格	Dual D-Type Flip-Flop
MM74HCT74MTC	FAIRCHILD	获取价格	MM74HCT74 Dual D-Type Flip-Flop with Preset and Clear
MM74HCT74MTC	ROCHESTER	获取价格	D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMO
MM74HCT74MTC	ONSEMI	获取价格	双路 D 类触发器，带预设和清除输入
MM74HCT74MTCX	FAIRCHILD	获取价格	D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMO

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