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MM74HC688SJ PDF预览

MM74HC688SJ

更新时间: 2024-11-15 23:02:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 比较器运算电路逻辑集成电路光电二极管
页数 文件大小 规格书
6页 89K
描述
8-Bit Magnitude Comparator (Equality Detector)

MM74HC688SJ 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:5.30 MM, EIAJ TYPE 2, SOP-20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.1
Is Samacsys:N其他特性:CASCADABLE
系列:HC/UHJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.6 mm
逻辑集成电路类型:MAGNITUDE COMPARATOR湿度敏感等级:1
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:2/6 V传播延迟(tpd):220 ns
认证状态:Not Qualified座面最大高度:2.1 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

MM74HC688SJ 数据手册

 浏览型号MM74HC688SJ的Datasheet PDF文件第2页浏览型号MM74HC688SJ的Datasheet PDF文件第3页浏览型号MM74HC688SJ的Datasheet PDF文件第4页浏览型号MM74HC688SJ的Datasheet PDF文件第5页浏览型号MM74HC688SJ的Datasheet PDF文件第6页 
September 1983  
Revised February 1999  
MM74HC688  
8-Bit Magnitude Comparator (Equality Detector)  
The comparator’s output can drive 10 low power Schottky  
General Description  
equivalent loads. This comparator is functionally and pin  
compatible to the 74LS688. All inputs are protected from  
damage due to static discharge by diodes to VCC and  
The MM74HC688 equality detector utilizes advanced sili-  
con-gate CMOS technology to compare bit for bit two 8-bit  
words and indicates whether or not they are equal. The  
P=Q output indicates equality when it is LOW. A single  
active low enable is provided to facilitate cascading of sev-  
eral packages and enable comparison of words greater  
than 8 bits.  
ground.  
Features  
Typical propagation delay: 20 ns  
Wide power supply range: 2–6V  
Low quiescent current: 80 µA (74 Series)  
Large output current: 4 mA (74 Series)  
Same as HC521  
This device is useful in memory block decoding applica-  
tions, where memory block enable signals must be gener-  
ated from computer address information.  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HC688WM  
MM74HC688SJ  
MM74HC688MTC  
MM74HC688N  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Diagram  
Pin Assignments for DIP  
Top View  
Truth Table  
Inputs  
Data  
P,Q  
Enable  
G
L
P = Q  
P = Q  
P > Q  
P < Q  
X
L
H
H
H
L
L
H
© 1999 Fairchild Semiconductor Corporation  
DS005018.prf  
www.fairchildsemi.com  

MM74HC688SJ 替代型号

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