是否Rohs认证: | 不符合 | 生命周期: | Obsolete |
包装说明: | DIP-14 | Reach Compliance Code: | unknown |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.44 |
Is Samacsys: | N | 系列: | HC/UH |
JESD-30 代码: | R-PDIP-T14 | JESD-609代码: | e0 |
长度: | 19.18 mm | 负载电容(CL): | 50 pF |
逻辑集成电路类型: | XNOR GATE | 功能数量: | 4 |
输入次数: | 2 | 端子数量: | 14 |
最高工作温度: | 85 °C | 最低工作温度: | -40 °C |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | DIP |
封装等效代码: | DIP14,.3 | 封装形状: | RECTANGULAR |
封装形式: | IN-LINE | 峰值回流温度(摄氏度): | NOT SPECIFIED |
电源: | 2/6 V | Prop。Delay @ Nom-Sup: | 151 ns |
传播延迟(tpd): | 30 ns | 认证状态: | Not Qualified |
施密特触发器: | NO | 座面最大高度: | 5.08 mm |
子类别: | Gates | 最大供电电压 (Vsup): | 6 V |
最小供电电压 (Vsup): | 2 V | 标称供电电压 (Vsup): | 5 V |
表面贴装: | NO | 技术: | CMOS |
温度等级: | INDUSTRIAL | 端子面层: | Tin/Lead (Sn/Pb) |
端子形式: | THROUGH-HOLE | 端子节距: | 2.54 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | NOT SPECIFIED |
宽度: | 7.62 mm | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
MM74HC7266N/A+ | TI |
获取价格 |
IC,LOGIC GATE,QUAD 2-INPUT XNOR,HC-CMOS,DIP,14PIN,PLASTIC | |
MM74HC73 | NSC |
获取价格 |
Dual J-K Flip-Flops with Clear | |
MM74HC73J | NSC |
获取价格 |
Dual J-K Flip-Flops with Clear | |
MM74HC73J/A+ | NSC |
获取价格 |
IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,14PIN,CERAMIC | |
MM74HC73J/A+ | TI |
获取价格 |
IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,14PIN,CERAMIC | |
MM74HC73M | TI |
获取价格 |
HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PL | |
MM74HC73M | NSC |
获取价格 |
IC HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, | |
MM74HC73M/A+ | TI |
获取价格 |
IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,SOP,14PIN,PLASTIC | |
MM74HC73MX | ROCHESTER |
获取价格 |
HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PL | |
MM74HC73MX | TI |
获取价格 |
HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PL |