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MM74C910N PDF预览

MM74C910N

更新时间: 2024-09-09 20:06:39
品牌 Logo 应用领域
美国国家半导体 - NSC 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 143K
描述
IC 64 X 4 STANDARD SRAM, 700 ns, PDIP18, DIP-18, Static RAM

MM74C910N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP18,.3Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:8.75最长访问时间:700 ns
其他特性:INPUT ADDRESS REGISTERI/O 类型:SEPARATE
JESD-30 代码:R-PDIP-T18JESD-609代码:e0
长度:21.78 mm内存密度:256 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
功能数量:1端口数量:1
端子数量:18字数:64 words
字数代码:64工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64X4输出特性:3-STATE
可输出:NO封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP18,.3
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:5.08 mm子类别:SRAMs
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MM74C910N 数据手册

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September 1989  
MM54C910/MM74C910 256 Bit TRI-STATE  
Random Access Read/Write Memory  
É
General Description  
The MM54C910/MM74C910 is a 64 word by 4-bit random  
access memory. Inputs consist of six address lines, four  
data input lines, a WE, and a ME line. The six address lines  
are internally decoded to select one of the 64 word loca-  
tions. An internal address register latches the address infor-  
mation on the positive to negative transition of ME. The  
TRI-STATE outputs allow for easy memory expansion.  
Outputs are in the TRI-STATE (Hi-Z) condition when the  
device is writing or disabled.  
Features  
Y
Supply voltage range  
High noise immunity  
TTL compatible fan out  
Input address register  
Low power consumption  
3.0V to 5.5V  
0.45V (typ.)  
Y
Y
Y
Y
CC  
1 TTL load  
Address Operation: Address inputs must be stable (t  
SA  
prior to the positive to negative transition of ME, and (t  
)
)
HA  
250 nW/package (typ.)  
(chip enabled or disabled)  
250 ns (typ.) at 5.0V  
after the positive to negative transition of ME. The address  
register holds the information and stable address inputs are  
not needed at any other time.  
Y
Y
Y
Fast access time  
TRI-STATE outputs  
High voltage inputs  
Write Operation: Data is written into memory at the select-  
ed address if WE goes low while ME is low. WE must be  
held low for t  
returns high.  
and data must remain stable t after WE  
HD  
WE  
Read Operation: Data is nondestructively read from  
a
memory location by an address operation with WE held  
high.  
Logic Diagrams  
Input Protection  
TL/F/5914–2  
TL/F/5914–1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/5914  
RRD-B30M105/Printed in U. S. A.  

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