MM54C165W-MIL

更新时间： 2024-01-27 20:00:53

品牌	Logo	应用领域
美国国家半导体 - NSC		移位寄存器
页数	文件大小	规格书
6页	137K
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数据手册

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MM54C165W-MIL 数据手册

December 1992

MM54C165/MM74C165

Parallel-Load 8-Bit Shift Register

General Description

Features

Wide supply voltage range

Guaranteed noise margin

High noise immunity

3V to 15V

The MM54C165/MM74C165 functions as an 8-bit parallel-

load, serial shift register. Data is loaded into the register

independent of the state of the clock(s) when PARALLEL

LOAD (PL) is low. Shifting is inhibited as long as PL is low.

0.45 V

(typ.)

Low power TTL compatibility

fan out of 2

driving 74L

Data is sequentially shifted from complementary outputs, Q

and Q , highest-order bit (P7) first. New serial data may be

Parallel loading independent of clock

Dual clock inputs

entered via the SERIAL DATA (Ds) input. Serial shifting oc-

curs on the rising edge of CLOCK1 or CLOCK2. Clock in-

puts may be used separately or together for combined

clocking from independent sources. Either clock input may

be used also as an active-low clock enable. To prevent dou-

ble-clocking when a clock input is used as an enable, the

enable must be changed to a high level (disabled) only while

the clock is high.

Fully static operation

Connection and Block Diagrams

Dual-In-Line Package

TL/F/5897–2

Order Number MM54C165* or MM74C165*

*Please look into Section 8, Appendix D

for availability of various package types.

TL/F/5897–1

Top View

TL/F/5897–3

1995 National Semiconductor Corporation

TL/F/5897

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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