MM54C173

更新时间： 2024-11-15 10:53:11

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器
页数	文件大小	规格书
6页	111K
描述
TRI-STATE Quad D Flip-Flop

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MM54C173 数据手册

February 1988

MM54C173/MM74C173 TRI-STATE Quad D Flip-Flop

Features

General Description

Supply voltage range

3V to 15V

The MM54C173/MM74C173 TRI-STATE quad D flip-flop is

a monolithic complementary MOS (CMOS) integrated circuit

constructed with N- and P-channel enhancement transis-

tors. The four D-type flip-flops operate synchronously from a

common clock. The TRI-STATE output allows the device to

be used in bus-organized systems.

Tenth power TTL compatible

Drive 2 LPTTL loads

High noise immunity

0.45 V

(typ.)

Low power

Medium speed operation

High impedance TRI-STATE

The outputs are placed in the TRI-STATE mode when either

of the two output disable pins are in the logic ‘‘1’’ level. The

input disable allows the flip-flops to remain in their present

states without disrupting the clock. If either of the two input

disables are taken to a logic ‘‘1’’ level, the Q outputs are fed

back to the inputs and in this manner the flip-flops do not

change state.

Input disable without gating the clock

Applications

Automotive

Alarm systems

Data terminals

Instrumentation

Medical electronics

Industrial electronics

Remote metering

Computers

Clearing is enabled by taking the input to a logic ‘’1’’ level.

Clocking occurs on the positive-going transition.

Connection Diagram

Dual-In-Line Package

TL/F/5898–2

Top View

Order Number MM54C173 or MM74C173

Truth Table

(Both Output Disables Low)

Data

Input

Data Input Disable

Output

Logic ‘‘1’’ on One or Both Inputs

Logic ‘‘0’’ on Both Inputs

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation

TL/F/5898

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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