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MKE1XZ128VLL7 PDF预览

MKE1XZ128VLL7

更新时间: 2024-11-14 02:52:23
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
82页 1585K
描述
Kinetis KE17Z/13Z/12Z with up to 256 KB Flash

MKE1XZ128VLL7 数据手册

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NXP Semiconductors  
Data Sheet: Technical Data  
KE1xZP100M72SF1  
Rev. 2, 09/2021  
Kinetis KE17Z/13Z/12Z with up to  
MKE1xZ256VLL7  
MKE1xZ256VLH7  
MKE1xZ128VLL7  
MKE1xZ128VLH7  
256 KB Flash  
Up to 72 MHz ARM® Cortex®-M0+ Based Microcontroller  
KE1xZ256 MCUs are the leading parts for the KE1xZ family  
based on ARM® Cortex®-M0+ core. Providing up to 256 KB  
flash, up to 48 KB RAM, and the complete set of analog/digital  
features, KE1xZ extends Kinetis E family to higher performance  
and broader scalability. Robust and enhanced TSIs provide high-  
level stability and accuracy to customer's HMI system. 1 Msps  
ADC and FlexTimer help build a perfect solution for BLDC motor  
control systems.  
100 LQFP (LL)  
14x14x1.4 mm P 0.5  
64 LQFP (LH)  
10x10x1.4 mm P 0.5  
Core Processor and System  
• ARM® Cortex®-M0+ core, supports up to 72 MHz  
frequency  
Mixed-signal analog  
• 1× 12-bit analog-to-digital converter (ADC) with up  
to 16 channel analog inputs per module, up to 1  
Msps  
• 1× high-speed analog comparators (CMP) with  
internal 8-bit digital to analog converter (DAC)  
• ARM Core based on the ARMv6 Architecture and  
Thumb®-2 ISA  
• Configurable Nested Vectored Interrupt Controller  
(NVIC)  
Timing and control  
• 8-channel DMA controller extended up to 63 channels  
with DMAMUX  
• 3× Flex Timers (FTM) for PWM generation, offering  
up to 8 standard channels  
Memory and memory interfaces  
• Up to 256 KB program flash  
• Up to 48 KB SRAM  
• 1× 16-bit Low-Power Timer (LPTMR) with flexible  
wake up control  
• 1× 32-bit Low-power Periodic Interrupt Timer (LPIT)  
with 4 channels  
• 128 Bytes flash cache  
Power management  
Reliability, safety and security  
• Low-power ARM Cortex-M0+ core with excellent  
energy efficiency  
• Power management controller (PMC) with multiple  
power modes: Run, Wait, Stop, VLPR, VLPW and  
VLPS  
• Supports clock gating for unused modules, and specific  
peripherals remain working in low power modes  
• POR, LVD/LVR  
• Cyclic Redundancy Check (CRC) generator module  
• 128-bit unique identification (ID) number  
• Internal watchdog (WDOG) with independent clock  
source  
• External watchdog monitor (EWM) module  
• ADC self calibration feature  
• On-chip clock loss monitoring  
Human-machine interface (HMI)  
Debug functionality  
• Supports up to 32 interrupt request (IRQ) sources  
• Up to 89 GPIO pins with interrupt functionality  
• 2 x 25ch Touch sensing input (TSI) module, each  
TSI has 12 mutual channels (up to 6 × 6ch matrix)  
and 3 shield channels  
• Serial Wire Debug (SWD) debug interface  
• Debug Watchpoint and Trace (DWT)  
• Micro Trace Buffer (MTB)  
NXP reserves the right to change the production detail specifications as may be  
required to permit improvements in the design of its products.  

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