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MH8S72DBFD-7 PDF预览

MH8S72DBFD-7

更新时间: 2024-02-11 02:02:57
品牌 Logo 应用领域
三菱 - MITSUBISHI /
页数 文件大小 规格书
56页 941K
描述
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MH8S72DBFD-7 技术参数

生命周期:Obsolete包装说明:DIMM, DIMM168
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.32风险等级:5.84
访问模式:DUAL BANK PAGE BURST最长访问时间:6 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N168
内存密度:603979776 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:72功能数量:1
端口数量:1端子数量:168
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX72
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM168
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:3.3 V认证状态:Not Qualified
刷新周期:4096自我刷新:YES
最大待机电流:0.034 A子类别:DRAMs
最大压摆率:1.015 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

MH8S72DBFD-7 数据手册

 浏览型号MH8S72DBFD-7的Datasheet PDF文件第2页浏览型号MH8S72DBFD-7的Datasheet PDF文件第3页浏览型号MH8S72DBFD-7的Datasheet PDF文件第4页浏览型号MH8S72DBFD-7的Datasheet PDF文件第5页浏览型号MH8S72DBFD-7的Datasheet PDF文件第6页浏览型号MH8S72DBFD-7的Datasheet PDF文件第7页 
MITSUBISHI LSIs  
Preliminary Spec.  
Some contents are subject to change without notice.  
MH8S72DBFD-7,-8  
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM  
DESCRIPTION  
The MH8S72DBFD is 8388608 - word x 72-bit Sy nchronous  
DRAM module. This consist of nine industry standard  
8M x 8 Sy nchronous DRAMs in TSOP.  
The TSOP on a card edge dual in-line package prov ides any  
application where high densities and large of quantities memory  
are required.  
85pin  
1pin  
This is a socket-ty pe memory module ,suitable f or easy  
interchange or addition of module.  
FEATURES  
94pin  
95pin  
10pin  
11pin  
CLK  
Access Time  
Max.  
Frequency  
Type name  
[component level]  
6ns (CL = 2, 3)  
6ns (CL = 3)  
MH8S72DBFD-7  
MH8S72DBFD-8  
100MHz  
100MHz  
Utilizes industry standard 8M X 8 Synchronous DRAMs in  
TSOP package , industry standard Resistered buffer in TSSOP  
package and industry standard PLL in TSSOP package  
Single 3.3V +/- 0.3V supply  
124pin  
125pin  
40pin  
41pin  
LVTTL Interface  
Burst length 1/2/4/8/Full Page(programmable)  
Burst W rite / Single W rite(programmable)  
Auto precharge / All bank precharge controlled by A10  
Auto refresh and Self refresh  
4096 refresh cycles every 64ms  
Discrete IC and module design conform to  
PC/100 specification.  
(module Spec. Rev. 1.2 and SPD 1.2A)  
APPLICATION  
84pin  
168pin  
Main memory or graphic memory in computer systems  
MITSUBISHI  
ELECTRIC  
30/Sep. /1999  
MIT-DS-0351-0.0  
1

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