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MEC1609I-PZP PDF预览

MEC1609I-PZP

更新时间: 2024-10-26 19:49:19
品牌 Logo 应用领域
美国微芯 - MICROCHIP 通信数据传输PC外围集成电路
页数 文件大小 规格书
13页 532K
描述
MIXED SIGNAL MOBILE EMBEDDED CON

MEC1609I-PZP 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:LFBGA-144
Reach Compliance Code:compliantFactory Lead Time:14 weeks
风险等级:5.74地址总线宽度:16
边界扫描:YES总线兼容性:I2C; LPC; PCI; SPI
通信协议:ASYNC, BIT, BYTE, UART最大数据传输速率:0.25 MBps
外部数据总线宽度:32JESD-30 代码:S-PBGA-B144
长度:7 mm低功率模式:YES
DMA 通道数量:8I/O 线路数量:115
串行 I/O 数:8端子数量:144
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA144,13x13,20封装形状:SQUARE
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH筛选级别:TS 16949
座面最大高度:1.2 mm最大压摆率:29 mA
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:0.5 mm
端子位置:BOTTOM宽度:7 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches:1

MEC1609I-PZP 数据手册

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MEC1609/MEC1609i  
Mixed Signal Mobile Embedded Flash ARC EC BC-Link/  
VLPC Base Component  
- Embedded Memory Interface  
Product Features  
Host Serial or Parallel IRQ Source  
Provides Two Windows to On-Chip SRAM for  
Host Access  
• 3.3V Operation  
• ACPI Compliant  
Two Register Mailbox Command Interface  
Host Access of Virtual Registers Without EC  
Intervention  
• LPC Interface  
- LPC I/O and Trusted Cycles Decoded  
• VTR (standby) and VBAT (Power Planes)  
- Mailbox Registers Interface  
-
Low Standby Current in Sleep Mode  
Thirty-two 8-Bit Scratch Registers  
Two Register Mailbox Command Interface  
Two Register SMI Source Interface  
• Configuration Register Set  
- Compatible with ISA Plug-and-Play Standard  
- EC-Programmable Base Address  
• ARC-625D Embedded Controller (EC)  
- ACPI Embedded Controller Interface  
Four Instances  
1 or 4 Byte Data transfer capable  
- 16 KB Single Cycle 32-bit Wide Dual-ported  
SRAM, Accessible as Closely Coupled Data  
Memory and Instruction Memory  
- ACPI Power Management Interface  
SCI Event-Generating Functions  
• Battery Backed Resources  
- Power-Fail Status Register  
- 32 KHz Clock Generator  
- 2 KB Instruction Cache and AHB Memory-  
mapped SPI Flash Read Controller  
- 32 x 32 x 64 Fast Multiply  
- Week Alarm Timer Interface with Program-  
mable Wake-up from 1ms to 45 Days  
- Divide Assist and Saturation Arithmetic  
- Maskable Interrupt Aggregator/Accelerator  
Interface  
- VBAT-Powered Control Interface  
- VBAT-Backed 64 Byte Memory  
- Maskable Hardware Wake-Up Events  
- Sleep mode  
• Three EC-based SMBus 2.0 Host Controllers  
- Allows Master or Dual Slave Operation  
- JTAG Debug Port, Includes JTAG Master  
- MCU Serial Debug Port  
- Controllers are Fully Operational on Standby  
Power  
- DMA-driven I2C Network Layer Hardware  
- I2C Datalink Compatibility Mode  
- Multi-Master Capable  
- 8-Channel DMA Interface Supports SMBus  
Controllers and EC/Host GP-SPI Controllers  
• Embedded Flash  
- 192 KB user space + 2kB info block, 32-bit  
Access, 35ns Access Time, 1 K Cycles  
Endurance  
- Supports Clock Stretching  
- Programmable Bus Speeds  
- 400 KHz Capable  
- Programmable by LPC, EC and JTAG Inter-  
faces  
- Hardware Bus Access “Fairness” Interface  
- SMBus Time-outs Interface  
- 8 x 3 x 3 Port Multiplexing  
• PECI Interface 2.0  
- Flash Security Enhancements  
4K Boot Block Protection  
Direct JTAG and Direct LPC-protected (2) Pages  
at or Near Top of Memory for Password  
Protection  
• 18 x 8 Interrupt Capable Multiplexed Keyboard  
Scan Matrix  
• Legacy Support  
• Three independent Hardware Driven PS/2 Ports  
- Fast GATEA20 & Fast CPU_RESET  
• System to EC Message Interface  
- 8042 Style Host Interface  
- Fully functional on Main and/or Suspend  
Power  
- PS/2 Edge Wake Capable  
• 115 General Purpose I/O Pins  
- 8 GPIO Pass-Through Port (GPTP)  
2014 Microchip Technology Inc.  
DS00001769A-page 1  

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