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MEC1621

更新时间： 2024-11-19 14:55:07
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
12页 546K
描述
MEC1621/MEC1621i is the mixed signal base?component of a multi-device advanced I/O controller arc

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MEC1621 数据手册

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MEC1621/MEC1621i  
Low Power 32-bit Microcontroller with Embedded Flash  
–Two Register Mailbox Command Interface  
–Host Access of Virtual Registers Without EC  
Product Features  
• 3.3V Operation  
Intervention  
• ACPI Compliant  
- Mailbox Registers Interface  
–Thirty-two 8-Bit Scratch Registers  
–Two Register Mailbox Command Interface  
–Two Register SMI Source Interface  
• LPC Interface  
- LPC I/O Cycles Decoded  
• VTR (standby) and VBAT (Power Planes)  
- ACPI Embedded Controller Interface  
-
Low Standby Current in Sleep Mode  
–Four Instances  
–1 or 4 Byte Full Duplex Bidirectional Data Transfer  
Capable  
• Configuration Register Set  
- Compatible with ISA Plug-and-Play Standard  
- EC-Programmable Base Address  
• ARC-625D Embedded Controller (EC)  
- ACPI Power Management Interface  
–SCI Event-Generating Functions  
- BIOS Debug Port  
- 16 KB Single Cycle 32-bit Wide Dual-ported  
SRAM, Accessible as Closely Coupled Data  
Memory and Instruction Memory  
–ISA Port 80 Plug-in Card Emulation  
–2 Instances  
–Time Stamping Option  
- 32 x 32 x 64 Fast Multiply  
• Battery Backed Resources  
- Power-Fail Status Register  
- 32 KHz Clock Generator  
- Divide Assist and Saturation Arithmetic  
- Maskable Interrupt Aggregator/Accelerator  
Interface  
- Week Alarm Timer Interface with Program-  
mable Wake-up from 1ms to 45 Days  
- Maskable Hardware Wake-Up Events  
- Sleep mode  
- VBAT-Powered Control Interface  
- JTAG Debug Port, Includes JTAG Master  
- MCU Serial Debug Port  
–6 Latched Inputs  
–GPIO Capable  
- 8-Channel DMA Interface Supports SMBus  
Controllers and EC/Host GP-SPI Controllers  
- VBAT-Backed 64 Byte Memory  
• Three EC-based SMBus 2.0 Host Controllers  
- Allows Master or Dual Slave Operation  
- Delay Register  
- Boot ROM  
- Controllers are Fully Operational on Standby  
Power  
• Embedded Flash  
- 192 KB user space 32-bit Access, 30 ns  
Access Time, 10 K Cycles Endurance  
- DMA-driven I2C Network Layer Hardware  
- I2C Datalink Compatibility Mode  
- Multi-Master Capable  
- 1 KB EEPROM Emulation, 40 ns Access  
Time, 250 K Cycles Endurance  
- Supports Clock Stretching  
- Programmable Bus Speeds  
- 400 KHz Capable  
- Programmable by LPC, EC and JTAG Inter-  
faces  
- Flash Security Enhancements  
- Hardware Bus Access “Fairness” Interface  
- SMBus Time-outs Interface  
- 12 Port Flexible Multiplexing  
- Port Isolation  
–4K Boot Block Protection  
–Direct JTAG and Direct LPC-protected (2) Pages at  
or Near Top of Memory for Password Protection  
• Legacy Support  
- Fast GATEA20 & Fast CPU_RESET  
• System to EC Message Interface  
- 8042 Style Host Interface  
- Embedded Memory Interface  
• PECI Interface 3.0  
• Keyboard Matrix Scan Interface  
- 18 x 8 Interrupt/Wake Capable Multiplexed  
Keyboard Scan Matrix  
–Host Serial or Parallel IRQ Source  
–Provides Two Windows to On-Chip SRAM for Host  
Access  
- Row Predrive Option  
2014 Microchip Technology Inc.  
DS00001774A-page 1  
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