Datasheet > MEC1633

MEC1633

更新时间： 2024-10-27 14:54:03

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
11页	307K
描述
MEC1633 is the mixed signal base?component of a multi-device advanced I/O controller architectur

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MEC1633 数据手册

MEC1633

Low Power 32-Bit Mobile Embedded Controller

• System to EC Message Interface

Product Features

- 8042 Style Host Interface

- Embedded Memory Interface

• 3.3V Operation

• ACPI Compliant

• LPC Interface

–

Host Serial or Parallel IRQ Source

Provides Two Windows to On-Chip SRAM for

Host Access

- Supports LPC Bus frequencies of 19.2MHz to

33MHz

–

Two Register Mailbox Command Interface

Host Access of Virtual Registers Without EC

Intervention

• VTR (standby) and VBAT Power Planes

Low Standby Current in Sleep Mode

- Mailbox Registers Interface

–

Thirty-two 8-Bit Scratch Registers

Two Register Mailbox Command Interface

Two Register SMI Source Interface

• Configuration Register Set

- Compatible with ISA Plug-and-Play Standard

- EC-Programmable Base Address

- ACPI Embedded Controller Interface

• ARC-625D Embedded Controller (EC)

–

Four Instances

1 or 4 Byte Data transfer capable

Full-duplex Register Access

- 16 KB Single Cycle 32-bit Wide Dual-ported

SRAM, Accessible as Closely Coupled Data

Memory and Instruction Memory

- 4KB Boot ROM

- ACPI Power Management Interface

–

SCI Event-Generating Functions

• Battery Backed Resources

- 32 x 32 → 64 Fast Multiply

- Divide Assist and Saturation Arithmetic

- Maskable Interrupt Aggregator/Accelerator

Interface

- Power-Fail Status Register

- 32 KHz Clock Generator

- Week Alarm Timer Interface with Program-

mable Wake-up from 1ms to 45 Days

- VBAT-Powered Control Interface

- Maskable Hardware Wake-Up Events

- Sleep mode

–

Six Wake-up Input Signals

Optional Latching of Wake-up Inputs

- JTAG Debug Port, Includes JTAG Master

- MCU Serial Debug Port

- 1μS Delay Register

- 10-Channel DMA Interface Supports SMBus

Controllers and EC/Host GP-SPI Controllers

- VBAT-Backed 64 Byte Memory

• Four EC-based SMBus 2.0 Host Controllers

- Allows Master or Dual Slave Operation

- Controllers are Fully Operational on Standby

Power

• Embedded Flash

- 192 KB user space, 32-bit Access, 10 K

Cycles Endurance

- Flash Security Enhancements

- DMA-driven I²C Network Layer Hardware

- I²C Datalink Compatibility Mode

- Multi-Master Capable

–

4K Boot Block Protection

- Supports Clock Stretching

–

Direct JTAG and Direct LPC-protected (2) Pages

at or Near Top of Memory for Password

Protection

- Programmable Bus Speed up to 400KHz

- Hardware Bus Access “Fairness” Interface

- SMBus Time-outs Interface

- Multiple Flash Programming Options

- AMD-TSI Port

- 12 Ports Assignable to Any Controller

- 3 SMBus Isolation Switches

–

JTAG programmable

BIOS programmable

Programmable by EC at Power-on Using UART

Programmable on a Gang Programmer via

Gang-programmer Interface

–

Three Pairs of Ports Can Be Joined

• PECI Interface 3.0

• Embedded Non-volatile Read/Write Memory

• 18 x 8 Interrupt Capable Multiplexed Keyboard

Scan Matrix

- 2 KB of EEPROM, Single Byte Access, 250K

Cycles Endurance

- 8-byte Block Erasable, 128 Blocks

- Independent of main Flash memory

- Optional Push-Pull Drive for Fast Signal

Switching

• Legacy Support

- Fast GATEA20 & Fast CPU_RESET

 2014 Microchip Technology Inc.

DS00001775B-page 1

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