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MCM6926WJ10 PDF预览

MCM6926WJ10

更新时间: 2024-11-10 19:23:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 输入元件信息通信管理静态存储器光电二极管输出元件内存集成电路
页数 文件大小 规格书
8页 149K
描述
Standard SRAM, 128KX8, 10ns, BICMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

MCM6926WJ10 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:SOJ,
针数:32Reach Compliance Code:unknown
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.84最长访问时间:10 ns
其他特性:TTL COMPATIBLE INPUTS/OUTPUTSJESD-30 代码:R-PDSO-J32
JESD-609代码:e0长度:20.96 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端口数量:1端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX8
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:3.75 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

MCM6926WJ10 数据手册

 浏览型号MCM6926WJ10的Datasheet PDF文件第2页浏览型号MCM6926WJ10的Datasheet PDF文件第3页浏览型号MCM6926WJ10的Datasheet PDF文件第4页浏览型号MCM6926WJ10的Datasheet PDF文件第5页浏览型号MCM6926WJ10的Datasheet PDF文件第6页浏览型号MCM6926WJ10的Datasheet PDF文件第7页 
Order this document  
by MCM6926/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM6926  
Product Preview  
128K x 8 Bit Fast Static Random  
Access Memory  
The MCM6926 is a 1,048,576 bit static random access memory organized as  
131,072wordsof8bits. Thisdeviceisfabricatedusinghighperformancesilicon–  
gate BiCMOS technology. Static design eliminates the need for external clocks  
or timing strobes.  
WJ PACKAGE  
400 MIL SOJ  
CASE 857A–02  
Output enable (G) is a special control feature that provides increased system  
flexibility and eliminates bus contention problems.  
PIN ASSIGNMENT  
This device meets JEDEC standards for functionality and revolutionary pinout,  
and is available in a 400 mil plastic small–outline J–leaded package.  
A
A
A
1
32  
31  
30  
29  
28  
27  
A
2
Single 3.3 V Power Supply  
A
A
3
Fully Static — No Clock or Timing Strobes Necessary  
All Inputs and Outputs Are TTL Compatible  
Three State Outputs  
Fast Access Times: 8, 10, 12, 15 ns  
Center Power and I/O Pins for Reduced Noise  
Fully 3.3 V BiCMOS  
A
A
4
G
E
5
DQ0  
DQ1  
DQ7  
DQ6  
6
7
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
V
V
8
SS  
CC  
V
V
9
SS  
CC  
DQ2  
DQ3  
W
DQ5  
DQ4  
A
10  
11  
12  
13  
14  
15  
16  
BLOCK DIAGRAM  
A
A
A
V
V
CC  
SS  
A
A
A
A
A
A
A
A
A
MEMORY  
ROW  
DECODER  
MATRIX  
512 ROWS x 256 x 8  
COLUMNS  
A
A
A
A
A
PIN NAMES  
A0 – A16 . . . . . . . . . . . . . Address Input  
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
W . . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . . . Output Enable  
DQ0 – DQ7 . . . . . . . . Data Input/Output  
DQ0  
COLUMN I/O  
INPUT  
DATA  
COLUMN DECODER  
V
CC  
V
SS  
. . . . . . . . . . + 3.3 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . Ground  
CONTROL  
DQ7  
A
A
A
A
A
A
A
A
E
W
G
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.  
REV 1  
1/2/96  
Motorola, Inc. 1996  

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