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MCM6709BRJ7R PDF预览

MCM6709BRJ7R

更新时间: 2024-11-17 22:23:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器光电二极管信息通信管理
页数 文件大小 规格书
7页 106K
描述
64K x 4 Bit Static RAM

MCM6709BRJ7R 技术参数

生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ,针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.83
Is Samacsys:N最长访问时间:7 ns
JESD-30 代码:R-PDSO-J28长度:18.415 mm
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:4功能数量:1
端口数量:1端子数量:28
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX4
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:3.75 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

MCM6709BRJ7R 数据手册

 浏览型号MCM6709BRJ7R的Datasheet PDF文件第2页浏览型号MCM6709BRJ7R的Datasheet PDF文件第3页浏览型号MCM6709BRJ7R的Datasheet PDF文件第4页浏览型号MCM6709BRJ7R的Datasheet PDF文件第5页浏览型号MCM6709BRJ7R的Datasheet PDF文件第6页浏览型号MCM6709BRJ7R的Datasheet PDF文件第7页 
Order this document  
by MCM6709BR/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM6709BR  
Product Preview  
64K x 4 Bit Static RAM  
The MCM6709BR is a 262,144 bit static random access memory organized as  
65,536 words of 4 bits. Static design eliminates the need for external clocks or  
timing strobes.  
J PACKAGE  
300 MIL SOJ  
CASE 810B–03  
Output enable (G) is a special control feature that provides increased system  
flexibility and eliminates bus contention problems.  
The MCM6709BR meets JEDEC standards and is available in a revolutionary  
pinout 300 mil, 28 lead plastic surface–mount SOJ package.  
PIN ASSIGNMENT  
Single 5 V ± 10% Power Supply  
Fully Static — No Clock or Timing Strobes Necessary  
All Inputs and Outputs are TTL Compatible  
Center Power and I/O Pins for Reduced Noise  
Three State Outputs  
Fast Access Times:  
MCM6709BR–6 = 6 ns  
MCM6709BR–7 = 7 ns  
MCM6709BR–8 = 8 ns  
A
A
1
2
3
4
5
6
7
8
9
10  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
A
A
A
A
A
A
E
G
DQ  
DQ  
V
V
CC  
SS  
V
V
CC  
SS  
BLOCK DIAGRAM  
DQ  
DQ  
A
A
A
A
A
W
A
11  
12  
18  
17  
A
A
A
A
MEMORY MATRIX  
512 ROWS x 128 x 4  
COLUMNS  
A
13  
14  
16  
15  
ROW  
DECODER  
A
A
A
A
A
A
NC  
PIN NAMES  
A . . . . . . . . . . . . . . . . . . . Address Inputs  
W . . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . . . Output Enable  
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
DQ . . . . . . . . . . . . . . . Data Input/Output  
DQ  
COLUMN I/O  
INPUT  
DATA  
CONTROL  
COLUMN DECODER  
V
CC  
V
SS  
. . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . Ground  
DQ  
NC . . . . . . . . . . . . . . . . . No Connection  
A
A
A
A
A
A
A
All power supply and ground pins must  
be connected for proper operation of the  
device.  
E
W
G
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.  
REV 2  
3/17/97  
Motorola, Inc. 1997  

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