Datasheet > MCM6709R

MCM6709R

更新时间： 2024-11-17 22:54:51

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
8页	150K
描述
64K x 4 Bit Static RAM

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数据手册

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MCM6709R 数据手册

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SEMICONDUCTOR TECHNICAL DATA

MCM6709R

64K x 4 Bit Static RAM

The MCM6709R is a 262,144 bit static random access memory organized as

65,536 words of 4 bits, fabricated using high–performance silicon–gate BiCMOS

technology. Static design eliminates the need for external clocks or timing

strobes.

Output enable (G) is a special control feature that provides increased system

flexibility and eliminates bus contention problems.

J PACKAGE

300 MIL SOJ

CASE 810B–03

The MCM6709R meets JEDEC standards and is available in a revolutionary

pinout 300 mil, 28 lead plastic surface–mount SOJ package.

PIN ASSIGNMENT

•

Single 5 V ± 10% Power Supply

Fully Static — No Clock or Timing Strobes Necessary

All Inputs and Outputs are TTL Compatible

Center Power and I/O Pins for Reduced Noise

Three State Outputs

Fast Access Times: MCM6709R–6 = 6 ns

MCM6709R–7 = 7 ns

A15

A14

A13

A12

MCM6709R–8 = 8 ns

DQ0

DQ3

BLOCK DIAGRAM

DQ1

DQ2

A11

A10

MEMORY MATRIX

512 ROWS x 128 x 4

COLUMNS

ROW

DECODER

•

PIN NAMES

A0 – A15 . . . . . . . . . . . . Address Inputs

W . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . Output Enable

E . . . . . . . . . . . . . . . . . . . . . . Chip Enable

DQ0 – DQ3 . . . . . . . . Data Input/Output

DQ0

COLUMN I/O

•

INPUT

DATA

CONTROL

•

COLUMN DECODER

•

. . . . . . . . . . . . + 5 V Power Supply

. . . . . . . . . . . . . . . . . . . . . . . Ground

DQ3

NC . . . . . . . . . . . . . . . . . No Connection

All power supply and ground pins must

be connected for proper operation of the

device.

REV 1

5/95

Motorola, Inc. 1995

MOTOROLA FAST SRAM

MCM6709R

12 3 4 5 6 7 8

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