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MCM6726BWJ8 PDF预览

MCM6726BWJ8

更新时间: 2024-11-18 21:16:39
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 信息通信管理静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 142K
描述
Standard SRAM, 128KX8, 8ns, BICMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

MCM6726BWJ8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:0.400 INCH, PLASTIC, SOJ-32Reach Compliance Code:unknown
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:8.79最长访问时间:8 ns
JESD-30 代码:R-PDSO-J32JESD-609代码:e0
长度:20.96 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端口数量:1
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX8输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:3.75 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.16 mmBase Number Matches:1

MCM6726BWJ8 数据手册

 浏览型号MCM6726BWJ8的Datasheet PDF文件第2页浏览型号MCM6726BWJ8的Datasheet PDF文件第3页浏览型号MCM6726BWJ8的Datasheet PDF文件第4页浏览型号MCM6726BWJ8的Datasheet PDF文件第5页浏览型号MCM6726BWJ8的Datasheet PDF文件第6页浏览型号MCM6726BWJ8的Datasheet PDF文件第7页 
Order this document  
by MCM6726B/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM6726B  
128K x 8 Bit Fast Static Random  
Access Memory  
The MCM6726B is a 1,048,576 bit static random access memory organized  
as 131,072 words of 8 bits. This device is fabricated using high performance sili-  
con–gate BiCMOS technology. Static design eliminates the need for external  
clocks or timing strobes.  
WJ PACKAGE  
400 MIL SOJ  
CASE 857A–02  
Output enable (G) is a special control feature that provides increased system  
flexibility and eliminates bus contention problems.  
This device meets JEDEC standards for functionality and revolutionary pinout,  
and is available in a 400 mil plastic small–outline J–leaded package.  
PIN ASSIGNMENT  
A
A
A
1
32  
31  
30  
29  
28  
27  
Single 5 V ± 10% Power Supply  
A
Fully Static — No Clock or Timing Strobes Necessary  
All Inputs and Outputs Are TTL Compatible  
Three State Outputs  
Fast Access Times: 8, 10, 12 ns  
Center Power and I/O Pins for Reduced Noise  
2
A
A
3
A
A
4
G
E
5
DQ0  
DQ1  
DQ7  
DQ6  
6
7
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
V
V
8
SS  
CC  
BLOCK DIAGRAM  
V
V
9
SS  
CC  
A
A
A
DQ2  
DQ3  
W
DQ5  
DQ4  
A
10  
11  
12  
13  
14  
15  
16  
V
V
CC  
SS  
A
MEMORY  
A
A
A
A
A
ROW  
DECODER  
MATRIX  
512 ROWS x 256 x 8  
COLUMNS  
A
A
A
A
A
A
A
A
PIN NAMES  
DQ0  
COLUMN I/O  
A0 – A16 . . . . . . . . . . . . . Address Input  
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
W . . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . . . Output Enable  
DQ0 – DQ7 . . . . . . . . Data Input/Output  
INPUT  
DATA  
CONTROL  
COLUMN DECODER  
DQ7  
A
A
A
A
A
A
A
A
V
CC  
V
SS  
. . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . Ground  
E
W
G
REV 2  
5/95  
Motorola, Inc. 1995  

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