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MCM6709BJ12R PDF预览

MCM6709BJ12R

更新时间: 2024-11-17 22:25:43
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
7页 106K
描述
64K x 4 Bit Static RAM

MCM6709BJ12R 技术参数

生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ,针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.83
最长访问时间:12 nsJESD-30 代码:R-PDSO-J28
长度:18.415 mm内存密度:262144 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
功能数量:1端口数量:1
端子数量:28字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX4输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:3.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

MCM6709BJ12R 数据手册

 浏览型号MCM6709BJ12R的Datasheet PDF文件第2页浏览型号MCM6709BJ12R的Datasheet PDF文件第3页浏览型号MCM6709BJ12R的Datasheet PDF文件第4页浏览型号MCM6709BJ12R的Datasheet PDF文件第5页浏览型号MCM6709BJ12R的Datasheet PDF文件第6页浏览型号MCM6709BJ12R的Datasheet PDF文件第7页 
Order this document  
by MCM6709B/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM6709B  
Product Preview  
64K x 4 Bit Static RAM  
The MCM6709B is a 262,144 bit static random access memory organized as  
65,536 words of 4 bit. Static design eliminates the need for external clocks or tim-  
ing strobes.  
Output enable (G), a special control feature of the MCM6709B, provides in-  
creased system flexibility and eliminates bus contention problems.  
The MCM6709B is available in a 300 mil, 28 lead plastic surface–mount SOJ  
package.  
J PACKAGE  
300 MIL SOJ  
CASE 810B–03  
Single 5 V ± 10% Power Supply  
Fully Static — No Clock or Timing Strobes Necessary  
All Inputs and Outputs are TTL Compatible  
Three State Outputs  
Fast Access Times: MCM6709B–8 = 8 ns  
MCM6709B–10 = 10 ns  
PIN ASSIGNMENT  
NC  
A
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
A
A
A
A
A
A
CC  
2
MCM6709B–12 = 12 ns  
A
3
A
4
A
5
A
6
BLOCK DIAGRAM  
A
7
A
A
8
NC  
NC  
DQ  
DQ  
DQ  
DQ  
W
A
A
A
9
A
10  
11  
12  
13  
14  
A
MEMORY MATRIX  
256 ROWS x 256 x 4  
COLUMNS  
A
A
ROW  
DECODER  
E
G
A
A
A
V
SS  
PIN NAMES  
DQ  
COLUMN I/O  
COLUMN DECODER  
INPUT  
DATA  
CONTROL  
A . . . . . . . . . . . . . . . . . . Address Inputs  
W . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . Output Enable  
E . . . . . . . . . . . . . . . . . . . . Chip Enable  
DQ . . . . . . . . . . . . . Data Input/Output  
. . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . Ground  
NC . . . . . . . . . . . . . . . . No Connection  
DQ  
A
A
A
A
A
A
A
A
V
CC  
V
SS  
E
W
G
This document contains informantion on a new product under development. Motorola reserves the right to change or discontinue this product without notice.  
REV 1  
10/9/96  
Motorola, Inc. 1996  

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