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SEMICONDUCTOR TECHNICAL DATA
MCM6709BR
Product Preview
64K x 4 Bit Static RAM
The MCM6709BR is a 262,144 bit static random access memory organized as
65,536 words of 4 bits. Static design eliminates the need for external clocks or
timing strobes.
J PACKAGE
300 MIL SOJ
CASE 810B–03
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6709BR meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 28 lead plastic surface–mount SOJ package.
PIN ASSIGNMENT
•
•
•
•
•
•
Single 5 V ± 10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs are TTL Compatible
Center Power and I/O Pins for Reduced Noise
Three State Outputs
Fast Access Times:
MCM6709BR–6 = 6 ns
MCM6709BR–7 = 7 ns
MCM6709BR–8 = 8 ns
A
A
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
22
21
20
19
A
A
A
A
A
A
E
G
DQ
DQ
V
V
CC
SS
V
V
CC
SS
BLOCK DIAGRAM
DQ
DQ
A
A
A
A
A
W
A
11
12
18
17
A
A
A
A
MEMORY MATRIX
512 ROWS x 128 x 4
COLUMNS
A
13
14
16
15
•
ROW
DECODER
A
A
A
A
A
•
•
A
NC
PIN NAMES
A . . . . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
DQ . . . . . . . . . . . . . . . Data Input/Output
DQ
•
•
•
COLUMN I/O
•
•
•
INPUT
DATA
CONTROL
•
•
•
COLUMN DECODER
V
CC
V
SS
. . . . . . . . . . . . + 5 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . Ground
DQ
NC . . . . . . . . . . . . . . . . . No Connection
A
A
A
A
A
A
A
All power supply and ground pins must
be connected for proper operation of the
device.
E
W
G
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2
3/17/97
Motorola, Inc. 1997
MOTOROLA FAST SRAM
MCM6709BR
1