Datasheet > MCM63P919ZP225

MCM63P919ZP225

更新时间： 2024-11-25 20:58:07

品牌	Logo	应用领域
恩智浦 - NXP		时钟静态存储器内存集成电路
页数	文件大小	规格书
30页	715K
描述
512KX18 CACHE SRAM, 2.6ns, PBGA119, BUMP, PLASTIC, BGA-119

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MCM63P919ZP225 技术参数

生命周期：	Transferred	零件包装代码：	BGA
包装说明：	BGA, BGA119,7X17,50	针数：	119
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.53
最长访问时间：	2.6 ns	最大时钟频率 (fCLK)：	225 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B119
长度：	22 mm	内存密度：	9437184 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
功能数量：	1	端子数量：	119
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	512KX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA119,7X17,50
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	SERIAL	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	2.4 mm
最小待机电流：	3.14 V	子类别：	SRAMs
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	宽度：	14 mm
Base Number Matches：	1

MCM63P919ZP225 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

MOTOROLA

Order this document

by MCM63P837/D

MCM63P837

MCM63P919

Product Preview

256K x 36 and 512K x 18 Bit

Pipelined BurstRAM

Synchronous Fast Static RAM

The MCM63P837 and MCM63P919 are 8M–bit synchronous fast static RAMs

designed to provide a burstable, high performance, secondary cache for the

PowerPC and other high performance microprocessors. The MCM63P837

(organized as 256K words by 36 bits) and the MCM63P919 (organized as 512K

words by 18 bits) are fabricated in Motorola’s high performance silicon gate

CMOS technology. Synchronous design allows precise cycle control with the use

of an external clock (K).

TQ PACKAGE

TQFP

CASE 983A–01

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K)

controlled through positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM63P837 and MCM63P919

(burstsequenceoperatesinlinearorinterleavedmodedependentuponthestate

of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

ZP PACKAGE

PBGA

CASE 999–02

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable (SW) are provided to allow writes to either individual bytes or

to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa, SBb

controls DQb, etc. Individual bytes are written if the selected byte writes SBx are

asserted with SW. All bytes are written if either SGW is asserted or if all SBx and

SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an

edge–triggeredoutput register and then released to the output buffers at the next

rising edge of clock (K).

The MCM63P837 and MCM63P919 operate from a 3.3 V core power supply.

All outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are

JEDEC standard JESD8–A and JESD8–5 compatible.

•

MCM63P837/MCM63P919–225 = 2.6 ns Access/4.4 ns Cycle (225 MHz)

MCM63P837/MCM63P919–200 = 3 ns Access/5 ns Cycle (200 MHz)

MCM63P837/MCM63P919–166 = 3.5 ns Access/6 ns Cycle (166 MHz)

3.3 V ±5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Single–Cycle Deselect Timing

Internally Self–Timed Write Cycle

•

Byte Write and Global Write Control

Sleep Mode (ZZ)

Simplified JTAG

JEDEC Standard 100–Pin TQFP and 119–Bump PBGA Packages

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 1

8/27/99

Motorola, Inc. 1999

MOTOROLA FAST SRAM

MCM63P837•MCM63P919

For More Information On This Product,

Go to: www.freescale.com

12 3 4 5 6 7...30

中文翻译

下载PDF

与MCM63P919ZP225相关器件

型号	品牌	获取价格	描述	数据表
MCM63P919ZP225R	MOTOROLA	获取价格	256K x 36 and 512K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63R736FC3	MOTOROLA	获取价格	Late-Write SRAM, 128KX36, 1.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP C
MCM63R736FC3.3	NXP	获取价格	128KX36 LATE-WRITE SRAM, 1.65ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, B
MCM63R736FC3.3	MOTOROLA	获取价格	128KX36 LATE-WRITE SRAM, 1.65ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, B
MCM63R736FC3.3R	MOTOROLA	获取价格	128KX36 LATE-WRITE SRAM, 1.65ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, B
MCM63R736FC3.7	NXP	获取价格	IC,SYNC SRAM,128KX36,CMOS,BGA,119PIN,PLASTIC
MCM63R736FC3.7R	NXP	获取价格	128KX36 LATE-WRITE SRAM, 1.85ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, B
MCM63R736FC3.7R	MOTOROLA	获取价格	128KX36 LATE-WRITE SRAM, 1.85ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, B
MCM63R736FC3R	NXP	获取价格	IC,SYNC SRAM,128KX36,CMOS,BGA,119PIN,PLASTIC
MCM63R736FC4	NXP	获取价格	IC,SYNC SRAM,128KX36,CMOS,BGA,119PIN,PLASTIC

与MCM63P919ZP225相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

39
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

31
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

59
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

55

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM63P919ZP225

MCM63P919ZP225 技术参数

MCM63P919ZP225 数据手册

与MCM63P919ZP225相关器件

与MCM63P919ZP225相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM63P919ZP225

MCM63P919ZP225 技术参数

MCM63P919ZP225 数据手册

与MCM63P919ZP225相关器件

与MCM63P919ZP225相关文章

您还可以找

您在本页遇到什么问题？