Datasheet > MCM63R818FC4R

MCM63R818FC4R

更新时间： 2024-11-22 07:27:39

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		静态存储器内存集成电路
页数	文件大小	规格书
21页	140K
描述
Late-Write SRAM, 256KX18, 2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, BGA-119

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MCM63R818FC4R 数据手册

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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by MCM63R736/D

MCM63R736

MCM63R818

4M Late Write HSTL

The MCM63R736/818 is a 4M–bit synchronous late write fast static RAM

designed to provide high performance in secondary cache and ATM switch,

Telecom, and other high speed memory applications. The MCM63R818

(organized as 256K words by 18 bits), and the MCM63R736 (organized as 128K

words by 36 bits) are fabricated in Motorola’s high performance silicon gate

copper CMOS technology.

The differential clock (CK) inputs control the timing of read/write operations of

theRAM. AttherisingedgeofCK, alladdresses, writeenables, andsynchronous

selects are registered. An internal buffer and special logic enable the memory to

accept write data on the rising edge of CK, a cycle after address and control sig-

nals. Read data is also driven on the rising edge of CK.

FC PACKAGE

FLIPPED CHIP PBGA

CASE 999E–01

The RAM uses HSTL inputs and outputs. The adjustable input trip–point (V

)

ref

and output voltage (V

) gives the system designer greater flexibility in

DDQ

optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or the

entire word.

The impedance of the output buffers is programmable, allowing the outputs to

match the impedance of the circuit traces which reduces signal reflections.

•

Byte Write Control

2.5 V –5% to 3.3 V +10% Operation

2.375 V to 3.6 V Operation

HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)

HSTL — User Selectable Input Trip–Point

HSTL — Compatible Programmable Impedance Output Drivers

Boundary Scan (JTAG) IEEE 1149.1 Compatible

Differential Clock Inputs

Optional x18 or x36 Organization

MCM63R736/818–3 = 3 ns

MCM63R736/818–3.3 = 3.3 ns

MCM63R736/818–3.7 = 3.7 ns

MCM63R736/818–4 = 4 ns

•

Sleep Mode Operation (ZZ pin)

119–Bump, 50 mil (1.27 mm) Pitch, 14mm x 22mm Flipped Chip Plastic

Ball Grid Array (PBGA) Package

10/12/00

Motorola, Inc. 2000

MOTOROLA FAST SRAM

MCM63R736•MCM63R818

12 3 4 5 6 7...21

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与MCM63R818FC4R相关器件

型号	品牌	获取价格	描述	数据表
MCM63R818FC5	MOTOROLA	获取价格	256KX18 LATE-WRITE SRAM, 2.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, BG
MCM63R818FC5R	MOTOROLA	获取价格	Late-Write SRAM, 256KX18, 2.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP C
MCM63R818RS3	MOTOROLA	获取价格	256KX18 LATE-WRITE SRAM, 1.5ns, CBGA119, FLIP CHIP, CERAMIC, BGA-119
MCM63R818RS3.3	MOTOROLA	获取价格	256KX18 LATE-WRITE SRAM, 1.65ns, CBGA119, FLIP CHIP, CERAMIC, BGA-119
MCM63R818RS3.3R	MOTOROLA	获取价格	256KX18 LATE-WRITE SRAM, 1.65ns, CBGA119, FLIP CHIP, CERAMIC, BGA-119
MCM63R818RS3.7	MOTOROLA	获取价格	Late-Write SRAM, 256KX18, 1.85ns, CMOS, CBGA119, FLIP CHIP, CERAMIC, BGA-119
MCM63R818RS3.7R	MOTOROLA	获取价格	Late-Write SRAM, 256KX18, 1.85ns, CMOS, CBGA119, FLIP CHIP, CERAMIC, BGA-119
MCM63R818RS3R	MOTOROLA	获取价格	256KX18 LATE-WRITE SRAM, 1.5ns, CBGA119, FLIP CHIP, CERAMIC, BGA-119
MCM63R818RS4	MOTOROLA	获取价格	Late-Write SRAM, 256KX18, 2ns, CMOS, CBGA119, FLIP CHIP, CERAMIC, BGA-119
MCM63R818RS4.4	MOTOROLA	获取价格	256KX18 LATE-WRITE SRAM, 2.2ns, CBGA119, FLIP CHIP, CERAMIC, BGA-119

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