Datasheet > MCM63R736FC3.3

MCM63R736FC3.3

更新时间： 2024-11-25 20:49:07

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		静态存储器内存集成电路
页数	文件大小	规格书
21页	140K
描述
128KX36 LATE-WRITE SRAM, 1.65ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, BGA-119

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中文翻译

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技术参数
数据手册

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MCM63R736FC3.3 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	BGA,	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.92	最长访问时间：	1.65 ns
JESD-30 代码：	R-PBGA-B119	JESD-609代码：	e0
长度：	22 mm	内存密度：	4718592 bit
内存集成电路类型：	LATE-WRITE SRAM	内存宽度：	36
功能数量：	1	端子数量：	119
字数：	131072 words	字数代码：	128000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	128KX36
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	2.77 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

MCM63R736FC3.3 数据手册

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM63R736/D

MCM63R736

MCM63R818

4M Late Write HSTL

The MCM63R736/818 is a 4M–bit synchronous late write fast static RAM

designed to provide high performance in secondary cache and ATM switch,

Telecom, and other high speed memory applications. The MCM63R818

(organized as 256K words by 18 bits), and the MCM63R736 (organized as 128K

words by 36 bits) are fabricated in Motorola’s high performance silicon gate

copper CMOS technology.

The differential clock (CK) inputs control the timing of read/write operations of

theRAM. AttherisingedgeofCK, alladdresses, writeenables, andsynchronous

selects are registered. An internal buffer and special logic enable the memory to

accept write data on the rising edge of CK, a cycle after address and control sig-

nals. Read data is also driven on the rising edge of CK.

FC PACKAGE

FLIPPED CHIP PBGA

CASE 999E–01

The RAM uses HSTL inputs and outputs. The adjustable input trip–point (V

)

ref

and output voltage (V

) gives the system designer greater flexibility in

DDQ

optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or the

entire word.

The impedance of the output buffers is programmable, allowing the outputs to

match the impedance of the circuit traces which reduces signal reflections.

•

Byte Write Control

2.5 V –5% to 3.3 V +10% Operation

2.375 V to 3.6 V Operation

HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)

HSTL — User Selectable Input Trip–Point

HSTL — Compatible Programmable Impedance Output Drivers

Boundary Scan (JTAG) IEEE 1149.1 Compatible

Differential Clock Inputs

Optional x18 or x36 Organization

MCM63R736/818–3 = 3 ns

MCM63R736/818–3.3 = 3.3 ns

MCM63R736/818–3.7 = 3.7 ns

MCM63R736/818–4 = 4 ns

•

Sleep Mode Operation (ZZ pin)

119–Bump, 50 mil (1.27 mm) Pitch, 14mm x 22mm Flipped Chip Plastic

Ball Grid Array (PBGA) Package

10/12/00

Motorola, Inc. 2000

MOTOROLA FAST SRAM

MCM63R736•MCM63R818

12 3 4 5 6 7...21

中文翻译

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与MCM63R736FC3.3相关器件

型号	品牌	获取价格	描述	数据表
MCM63R736FC3.3R	MOTOROLA	获取价格	128KX36 LATE-WRITE SRAM, 1.65ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, B
MCM63R736FC3.7	NXP	获取价格	IC,SYNC SRAM,128KX36,CMOS,BGA,119PIN,PLASTIC
MCM63R736FC3.7R	NXP	获取价格	128KX36 LATE-WRITE SRAM, 1.85ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, B
MCM63R736FC3.7R	MOTOROLA	获取价格	128KX36 LATE-WRITE SRAM, 1.85ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, B
MCM63R736FC3R	NXP	获取价格	IC,SYNC SRAM,128KX36,CMOS,BGA,119PIN,PLASTIC
MCM63R736FC4	NXP	获取价格	IC,SYNC SRAM,128KX36,CMOS,BGA,119PIN,PLASTIC
MCM63R736FC4.4R	MOTOROLA	获取价格	Late-Write SRAM, 128KX36, 2.2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP C
MCM63R736FC4R	NXP	获取价格	IC,SYNC SRAM,128KX36,CMOS,BGA,119PIN,PLASTIC
MCM63R736FC5	MOTOROLA	获取价格	Late-Write SRAM, 128KX36, 2.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP C
MCM63R736FC5R	MOTOROLA	获取价格	Late-Write SRAM, 128KX36, 2.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP C

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