5秒后页面跳转
MCM63P919TQ225R PDF预览

MCM63P919TQ225R

更新时间: 2024-11-22 00:48:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
30页 719K
描述
256K x 36 and 512K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM63P919TQ225R 数据手册

 浏览型号MCM63P919TQ225R的Datasheet PDF文件第2页浏览型号MCM63P919TQ225R的Datasheet PDF文件第3页浏览型号MCM63P919TQ225R的Datasheet PDF文件第4页浏览型号MCM63P919TQ225R的Datasheet PDF文件第5页浏览型号MCM63P919TQ225R的Datasheet PDF文件第6页浏览型号MCM63P919TQ225R的Datasheet PDF文件第7页 
Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
MOTOROLA  
Order this document  
by MCM63P837/D  
MCM63P837  
MCM63P919  
Product Preview  
256K x 36 and 512K x 18 Bit  
Pipelined BurstRAM  
Synchronous Fast Static RAM  
The MCM63P837 and MCM63P919 are 8M–bit synchronous fast static RAMs  
designed to provide a burstable, high performance, secondary cache for the  
PowerPC and other high performance microprocessors. The MCM63P837  
(organized as 256K words by 36 bits) and the MCM63P919 (organized as 512K  
words by 18 bits) are fabricated in Motorola’s high performance silicon gate  
CMOS technology. Synchronous design allows precise cycle control with the use  
of an external clock (K).  
TQ PACKAGE  
TQFP  
CASE 983A–01  
Addresses (SA), data inputs (DQx), and all control signals except output  
enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K)  
controlled through positive–edge–triggered noninverting registers.  
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst  
addresses can be generated internally by the MCM63P837 and MCM63P919  
(burstsequenceoperatesinlinearorinterleavedmodedependentuponthestate  
of LBO) and controlled by the burst address advance (ADV) input pin.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
ZP PACKAGE  
PBGA  
CASE 999–02  
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-  
nous write enable (SW) are provided to allow writes to either individual bytes or  
to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa, SBb  
controls DQb, etc. Individual bytes are written if the selected byte writes SBx are  
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and  
SW are asserted.  
For read cycles, pipelined SRAMs output data is temporarily stored by an  
edge–triggeredoutput register and then released to the output buffers at the next  
rising edge of clock (K).  
The MCM63P837 and MCM63P919 operate from a 3.3 V core power supply.  
All outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are  
JEDEC standard JESD8–A and JESD8–5 compatible.  
MCM63P837/MCM63P919–225 = 2.6 ns Access/4.4 ns Cycle (225 MHz)  
MCM63P837/MCM63P919–200 = 3 ns Access/5 ns Cycle (200 MHz)  
MCM63P837/MCM63P919–166 = 3.5 ns Access/6 ns Cycle (166 MHz)  
3.3 V ±5% Core Power Supply, 2.5 V or 3.3 V I/O Supply  
ADSP, ADSC, and ADV Burst Control Pins  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Single–Cycle Deselect Timing  
Internally Self–Timed Write Cycle  
Byte Write and Global Write Control  
Sleep Mode (ZZ)  
Simplified JTAG  
JEDEC Standard 100–Pin TQFP and 119–Bump PBGA Packages  
The PowerPC name is a trademark of IBM Corp., used under license therefrom.  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
REV 1  
8/27/99  
Motorola, Inc. 1999  
For More Information On This Product,  
Go to: www.freescale.com  

与MCM63P919TQ225R相关器件

型号 品牌 获取价格 描述 数据表
MCM63P919ZP166 MOTOROLA

获取价格

256K x 36 and 512K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P919ZP166R NXP

获取价格

512KX18 CACHE SRAM, 3.5ns, PBGA119, BUMP, PLASTIC, BGA-119
MCM63P919ZP166R MOTOROLA

获取价格

256K x 36 and 512K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P919ZP200 NXP

获取价格

512KX18 CACHE SRAM, 3ns, PBGA119, BUMP, PLASTIC, BGA-119
MCM63P919ZP200 MOTOROLA

获取价格

256K x 36 and 512K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P919ZP200R MOTOROLA

获取价格

256K x 36 and 512K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P919ZP225 NXP

获取价格

512KX18 CACHE SRAM, 2.6ns, PBGA119, BUMP, PLASTIC, BGA-119
MCM63P919ZP225 MOTOROLA

获取价格

256K x 36 and 512K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P919ZP225R MOTOROLA

获取价格

256K x 36 and 512K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63R736FC3 MOTOROLA

获取价格

Late-Write SRAM, 128KX36, 1.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP C