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MCM63P531

更新时间: 2024-11-24 22:54:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
16页 337K
描述
32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM63P531 数据手册

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Order this document  
by MCM63P531/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM63P531  
Advance Information  
32K x 32 Bit Pipelined BurstRAM  
Synchronous Fast Static RAM  
The MCM63P531 is a 1M bit synchronous fast static RAM designed to provide  
a burstable, high performance, secondary cache for the 68K Family, PowerPC ,  
and Pentium microprocessors. It is organized as 32K words of 32 bits each,  
fabricated using high performance silicon gate CMOS technology. This device  
integrates input registers, an output register, a 2–bit address counter, and high  
speed SRAM onto a single monolithic circuit for reduced parts count in cache  
dataRAMapplications. Synchronousdesignallowsprecisecyclecontrolwiththe  
use of an external clock (K). CMOS circuitry reduces the overall power consump-  
tion of the integrated functions for greater reliability.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
Addresses (SA), data inputs (DQx), and all control signals except output en-  
able (G) and Linear Burst Order (LBO) are clock (K) controlled through positive–  
edge–triggered noninverting registers.  
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst  
addresses can be generated internally by the MCM63P531 (burst sequence op-  
eratesinlinearorinterleavedmodedependentuponstateofLBO) and controlled  
by the burst address advance (ADV) input pin.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-  
nous write enable SW are provided to allow writes to either individual bytes or to  
all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls  
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte  
writes SBx are asserted with SW. All bytes are written if either SGW is asserted  
or if all SBx and SW are asserted.  
For read cycles, pipelined SRAMs output data is temporarily stored by an  
edge–triggeredoutput register and then released to the output buffers at the next  
rising edge of clock (K).  
The MCM63P531 operates from a 3.3 V power supply, all inputs and outputs  
are LVTTL compatible.  
MCM63P531–4.5 = 4.5 ns access / 10 ns cycle  
MCM63P531–7 = 7 ns access / 13.3 ns cycle  
MCM63P531–8 = 8 ns access / 15 ns cycle  
MCM63P531–9 = 9 ns access / 16.6 ns cycle  
Single 3.3 V + 10%, – 5% Power Supply  
ADSP, ADSC, and ADV Burst Control Pins  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Internally Self–Timed Write Cycle  
Byte Write and Global Write Control  
Sleep Mode (ZZ)  
Intel PBSRAM 2.0 Compliant  
Single–Cycle Deselect Timing  
100 Pin TQFP Package  
BurstRAM is a trademark of Motorola, Inc.  
PowerPC is a trademark of IBM Corp.  
Pentium is a trademark of Intel Corp.  
This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.  
6/21/96  
Motorola, Inc. 1996  

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