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MCM63P631ATQ117R PDF预览

MCM63P631ATQ117R

更新时间: 2024-10-01 22:05:55
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摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
16页 232K
描述
64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM63P631ATQ117R 数据手册

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Order this document  
by MCM63P631A/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM63P631A  
Product Preview  
64K x 32 Bit Pipelined BurstRAM  
Synchronous Fast Static RAM  
The MCM63P631A is a 2M bit synchronous fast static RAM designed to pro-  
vide a burstable, high performance, secondary cache for the 68K Family, Pow-  
erPC , and Pentium microprocessors. It is organized as 64K words of 32 bits  
each. This device integrates input registers, an output register, a 2–bit address  
counter, and high speed SRAM onto a single monolithic circuit for reduced parts  
count in cache data RAM applications. Synchronous design allows precise cycle  
control with the use of an external clock (K). CMOS circuitry reduces the overall  
power consumption of the integrated functions for greater reliability.  
Addresses (SA), data inputs (DQx), and all control signals except output  
enable (G), sleep mode (ZZ), and Linear Burst Order (LBO) are clock (K) con-  
trolled through positive–edge–triggered noninverting registers.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst  
addresses can be generated internally by the MCM63P631A (burst sequence  
operates in linear or interleaved mode dependent upon state of LBO) and con-  
trolled by the burst address advance (ADV) input pin.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-  
nous write enable SW are provided to allow writes to either individual bytes or to  
all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls  
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte  
writes SBx are asserted with SW. All bytes are written if either SGW is asserted  
or if all SBx and SW are asserted.  
For read cycles, pipelined SRAMs output data is temporarily stored by an  
edge–triggeredoutput register and then released to the output buffers at the next  
rising edge of clock (K).  
The MCM63P631A operates from a 3.3 V power supply, all inputs and outputs  
are LVTTL compatible.  
MCM63P631A–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)  
MCM63P631A–100 = 4.5 ns access / 10 ns cycle (100 MHz)  
MCM63P631A–75 = 7 ns access / 13.3 ns cycle (75 MHz)  
MCM63P631A–66 = 8 ns access / 15 ns cycle (66 MHz)  
Single 3.3 V + 10%, – 5% Power Supply  
ADSP, ADSC, and ADV Burst Control Pins  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Internally Self–Timed Write Cycle  
Byte Write and Global Write Control  
Sleep Mode (ZZ)  
PB1 Version 2.0 Compatible  
Single–Cycle Deselect Timing  
JEDEC Standard 100–Pin TQFP Package  
The PowerPC name is a trademark of IBM Corp., used under license therefrom.  
Pentium is a trademark of Intel Corp.  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
9/30/97  
Motorola, Inc. 1997  

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