Datasheet > MCM63P636

MCM63P636

更新时间： 2024-11-26 22:54:51

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
27页	332K
描述
64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

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MCM63P636 数据手册

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SEMICONDUCTOR TECHNICAL DATA

MCM63P636

Advance Information

64K x 36 Bit Pipelined BurstRAM

Synchronous Fast Static RAM

TheMCM63P636isa2M–bitsynchronousfaststaticRAMdesignedtoprovide

burstable, high performance, secondary cache for advanced microprocessors.

It is organized as 64K words of 36 bits each. This device integrates input regis-

ters, an output register, a 2–bit address counter, and a high speed SRAM onto

a single monolithic circuit for reduced parts count in cache data RAM applica-

tions. Synchronous design allows for precise cycle control with the use of an ex-

ternal clock (K) and external strobe clock (SK).

ZP PACKAGE

PBGA

CASE 1107–01

Addresses (SA), data inputs (DQx), and all control signals are clock (K)

controlled through positive–edge–triggered noninverting registers. Data strobes

STRBA, STRBA, STRBB, and STRBB are strobe clock (SK) controlled through

positive–edge–triggered non–inverting registers. Strobe clock, 180 degrees out

of phase with clock (K), is only used with the data strobes such that they are

centered with data output on read cycles.

TQ PACKAGE

TQFP

CASE 983A–01

Burst sequences are initiated with ADS input pin, and subsequent burst

addresses are generated internally by MCM63P636.

Write cycles are internally self–timed and are initiated with address and control

logic by the rising edge of the clock (K) input. This feature eliminates complex

off–chip write pulse generation and provides increased timing flexibility for

incoming signals. Special logic enables the memory to accept data on the rising

edge of clock (K) a cycle after address and control signals.

For read cycles, the SRAMs output data is temporarily stored by an

edge–triggered output register and then released to the output buffers at the

second rising edge of clock (K) for a read latency of three cycles. Data strobes

rise and fall with SRAM output to help external devices receiving the data to

latch the data.

TheMCM63P636operatesfroma3.3Vcorepowersupply, a2.0Vinputpower

supply, and a 2.0 V I/O power supply. These power supplies are designed so that

power sequencing is not required.

•

MCM63P636–250 = 3.9 ns Access/4 ns Cycle (250 MHz)

MCM63P636–225 = 4.3 ns Access/4.4 ns Cycle (225 MHz)

MCM63P636–200 = 4.9 ns Access/5 ns Cycle (200 MHz)

•

3.3 V ± 200 mV V

Internally Self–Timed Late Write Cycle

Three–Cycle Single–Read Latency

Strobe Clock Input and Data Strobe Output Pins

On–Chip Output Enable Control

On–Chip Burst Advance Control

Four–Tick Burst

Power–On Reset Pin

Low Power Stop Clock Operation

Boundary Scan (PBGA Only)

Supply, 2.0 V V

and V

Supply

DDQ

DDI

JEDEC Standard 153–Pin PBGA and 100–Pin TQFP Packages

This document contains information on a new product. Specifications and information herein are subject to change without notice.

3/16/98

Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM63P636

12 3 4 5 6 7...27

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与MCM63P636相关器件

型号	品牌	获取价格	描述	数据表
MCM63P636TQ200	MOTOROLA	获取价格	64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P636TQ200R	MOTOROLA	获取价格	64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P636ZP200	MOTOROLA	获取价格	64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P636ZP200R	MOTOROLA	获取价格	64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P636ZP225	MOTOROLA	获取价格	64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P636ZP225R	MOTOROLA	获取价格	64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P636ZP250	MOTOROLA	获取价格	64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P636ZP250R	MOTOROLA	获取价格	64K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P733A	MOTOROLA	获取价格	128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P733ATQ100	MOTOROLA	获取价格	128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

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