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MCM63L918AFC4.5 PDF预览

MCM63L918AFC4.5

更新时间： 2024-11-25 15:41:11
品牌 Logo 应用领域
恩智浦 - NXP 静态存储器内存集成电路
页数 文件大小 规格书
20页 507K
描述
IC,SYNC SRAM,512KX18,CMOS,BGA,119PIN,PLASTIC

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MCM63L918AFC4.5 技术参数

生命周期：Transferred零件包装代码：BGA
包装说明：BGA,针数：119
Reach Compliance Code：unknown风险等级：5.64
最长访问时间：4.5 nsJESD-30 代码：R-PBGA-B119
长度：22 mm内存密度：9437184 bit
内存集成电路类型：LATE-WRITE SRAM内存宽度：18
功能数量：1端子数量：119
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX18
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：2.77 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
宽度：14 mmBase Number Matches：1

MCM63L918AFC4.5 数据手册

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Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MCM63L836A/D  
MCM63L836A  
MCM63L918A  
Advance Information  
8M Late Write HSTL  
The MCM63L836A/918A is an 8M–bit synchronous late write fast static RAM  
designed to provide high performance in secondary cache and ATM switch,  
Telecom, and other high speed memory applications. The MCM63L918A  
(organized as 512K words by 18 bits) and the MCM63L836A (organized as 256K  
words by 36 bits) are fabricated in Motorola’s high performance silicon gate  
copper CMOS technology.  
The differential clock (CK) inputs control the timing of read/write operations of  
theRAM. AttherisingedgeofCK, alladdresses, writeenables, andsynchronous  
selects are registered. An internal buffer and special logic enable the memory to  
accept write data on the rising edge of CK, a cycle after address and control  
signals. Read data is available at the falling edge of CK.  
FC PACKAGE  
PBGA  
CASE 999D–01  
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (V  
)
ref  
and output voltage (V  
) gives the system designer greater flexibility in  
DDQ  
optimizing system performance.  
The synchronous write and byte enables allow writing to individual bytes or  
the entire word.  
The impedance of the output buffers is programmable, allowing the outputs to  
match the impedance of the circuit traces which reduces signal reflections.  
•
•
•
•
•
•
•
•
•
•
Byte Write Control  
Single 3.3 V ±10% Operation  
HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)  
HSTL — User Selectable Input Trip–Point  
HSTL — Compatible Programmable Impedance Output Drivers  
Register to Latch Synchronous Operation  
Boundary Scan (JTAG) IEEE 1149.1 Compatible  
Differential Clock Inputs  
Optional x18 or x36 Organization  
MCM63L836A/918A–3.8 = 3.8 ns  
MCM63L836A/918A–4.0 = 4.0 ns  
MCM63L836A/918A–4.2 = 4.2 ns  
MCM63L836A/918A–4.5 = 4.5 ns  
MCM63L836A/918A–5.0 = 5.0 ns  
•
•
Sleep Mode Operation (ZZ Pin)  
119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip Plastic  
Ball Grid Array (PBGA) Package  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
8/4/99  
Motorola, Inc. 1999  
For More Information On This Product,  
Go to: www.freescale.com  
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