Datasheet > MCM63F737ZP8.5R

MCM63F737ZP8.5R

更新时间： 2024-11-12 04:50:35

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		静态存储器内存集成电路
页数	文件大小	规格书
21页	320K
描述
Cache SRAM, 128KX36, 8.5ns, CMOS, PBGA119, PLASTIC, BGA-119

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技术参数
数据手册

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MCM63F737ZP8.5R 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	BGA,	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.19	最长访问时间：	8.5 ns
其他特性：	FLOW-THROUGH ARCHITECTURE	JESD-30 代码：	R-PBGA-B119
JESD-609代码：	e0	长度：	22 mm
内存密度：	4718592 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	36	功能数量：	1
端子数量：	119	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	128KX36	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	2.4 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
宽度：	14 mm

MCM63F737ZP8.5R 数据手册

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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by MCM63F737/D

MCM63F737

MCM63F819

128K x 36 and 256K x 18 Bit

Flow–Through BurstRAM

Synchronous Fast Static RAM

The MCM63F737 and MCM63F819 are 4M–bit synchronous fast static RAMs

designed to provide a burstable, high performance, secondary cache for the

PowerPC and other high performance microprocessors. The MCM63F737 is

organized as 128K words of 36 bits each and the MCM63F819 is organized as

256K words of 18 bits each. These devices integrate input registers, a 2–bit

address counter, and high speed SRAM onto a single monolithic circuit for

reduced parts count in cache data RAM applications. Synchronous design

allows precise cycle control with the use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output

enable(G), sleepmode(ZZ), andlinearburstorder(LBO)areclock(K)controlled

through positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM63F737 and MCM63F819

(burstsequenceoperatesinlinearorinterleavedmodedependentuponthestate

of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

TQ PACKAGE

TQFP

CASE 983A–01

ZP PACKAGE

PBGA

CASE 999–02

Synchronous byte write (SBx), synchronous global write (SGW), and

synchronous write enable (SW) are provided to allow writes to either individual

bytes or to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa,

SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx

are asserted with SW. All bytes are written if either SGW is asserted or if all SBx

and SW are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

from the memory array.

The MCM63F737 and MCM63F819 operate from a 3.3 V core power supply

and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs

are JEDEC standard JESD8–5 compatible.

•

MCM63F737/MCM63F819–8.5 = 8.5 ns Access

MCM63F737/MCM63F819–9 ns = 9 ns Access

MCM63F737/MCM63F810–10 ns = 10 ns Access

3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Single–Cycle Deselect Timing

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

Sleep Mode (ZZ)

JEDEC Standard 100–Pin TQFP and 119–Pin PBGA Packages

•

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

REV 2

3/12/99

Motorola, Inc. 1999

MOTOROLA FAST SRAM

MCM63F737•MCM63F819

12 3 4 5 6 7...21

中文翻译

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与MCM63F737ZP8.5R相关器件

型号	品牌	获取价格	描述	数据表
MCM63F737ZP9	NXP	获取价格	128KX36 CACHE SRAM, 9ns, PBGA119, 7 X 17 MM, PLASTIC, BGA-119
MCM63F737ZP9R	MOTOROLA	获取价格	Cache SRAM, 128KX36, 9ns, CMOS, PBGA119, PLASTIC, BGA-119
MCM63F819K	FREESCALE	获取价格	128K x 36 and 256K x 18 Bit Flow–Through Burs
MCM63F819KTQ11	FREESCALE	获取价格	128K x 36 and 256K x 18 Bit Flow–Through Burs
MCM63F819KTQ11	NXP	获取价格	256KX18 CACHE SRAM, 11ns, PQFP100, PLASTIC, TQFP-100
MCM63F819KTQ11R	FREESCALE	获取价格	128K x 36 and 256K x 18 Bit Flow–Through Burs
MCM63F819KTQ11R	NXP	获取价格	256KX18 CACHE SRAM, 11ns, PQFP100, PLASTIC, TQFP-100
MCM63F819KTQ8.5	FREESCALE	获取价格	128K x 36 and 256K x 18 Bit Flow–Through Burs
MCM63F819KTQ8.5	NXP	获取价格	256KX18 CACHE SRAM, 8.5ns, PQFP100, PLASTIC, TQFP-100
MCM63F819KTQ8.5R	NXP	获取价格	256KX18 CACHE SRAM, 8.5ns, PQFP100, PLASTIC, TQFP-100

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