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MCM56824AFN25AZP25 PDF预览

MCM56824AFN25AZP25

更新时间： 2024-11-10 22:05:27
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
10页 151K
描述
8K x 24 Bit Fast Static RAM

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MCM56824AFN25AZP25 数据手册

 浏览型号MCM56824AFN25AZP25的Datasheet PDF文件第2页浏览型号MCM56824AFN25AZP25的Datasheet PDF文件第3页浏览型号MCM56824AFN25AZP25的Datasheet PDF文件第4页浏览型号MCM56824AFN25AZP25的Datasheet PDF文件第5页浏览型号MCM56824AFN25AZP25的Datasheet PDF文件第6页浏览型号MCM56824AFN25AZP25的Datasheet PDF文件第7页 
Order this document  
by MCM56824A/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM56824A  
DSPRAM  
8K x 24 Bit Fast Static RAM  
The MCM56824A is a 196,608 bit static random access memory organized as  
8,192 words of 24 bits. The device integrates an 8K x 24 SRAM core with multiple  
chipenableinputs, outputenable, andanexternallycontrolledsingleaddresspin  
multiplexer. These functions allow for direct connection to the Motorola  
DSP56001 Digital Signal Processor and provide a very efficient means for imple-  
mentation of a reduced parts count system requiring noadditionalinterfacelogic.  
The availability of multiple chip enable (E1 and E2) and output enable (G) in-  
puts provides for greater system flexibility when multiple devices are used. With  
either chip enable input unasserted, the device will enter standby mode, useful  
inlow–powerapplications. Asingleon–chipmultiplexerselectsA12orX/Yasthe  
highest order address input depending upon the state of the V/S control input.  
This feature allows one physical static RAM component to efficiently store pro-  
gram and vector or scalar operands by dynamically re–partitioning the RAM  
array. Typical applications will logically map vector operands into upper memory  
with scalar operands being stored in lower memory. By connecting  
DSP56001address A15 to the VECTOR/SCALAR (V/S) MUX control  
pin, such partitioning can occur with no additional components. This al-  
lows efficient utilization of the RAM resource irrespective of operand  
FN PACKAGE  
52–LEAD PLCC  
CASE 778–02  
9 x 10 GRID  
86 BUMP PBGA  
CASE 896A–01  
PIN ASSIGNMENTS  
PLCC  
7
6
5
4
3
2
1
52 51 50 49 48 47  
46  
DQ0  
8
9
DQ23  
DQ22  
DQ21  
type. See application diagrams at the end of this document for addition-  
al information.  
Multiplepowerandgroundpinshavebeenutilizedtominimizeeffects  
induced by output noise.  
The MCM56824A is available in a 52 pin plastic leaded chip–carrier  
(PLCC) and a 9 x 10 grid, 86 bump surface mount PBGA.  
45  
44  
43  
42  
DQ1  
DQ2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
V
V
DQ20  
SS  
SS  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
41  
40  
39  
38  
37  
36  
35  
34  
DQ19  
DQ18  
DQ17  
DQ16  
DQ15  
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 10% Power Supply  
Fast Access and Cycle Times: 20/25/35 ns Max  
Fully Static Read and Write Operations  
Equal Address and Chip Enable Access Times  
Single Bit On–Chip Address Multiplexer  
Active High and Active Low Chip Enable Inputs  
Output Enable Controlled Three State Outputs  
High Board Density PLCC Package  
Low Power Standby Mode  
V
DQ9  
V
SS  
SS  
DQ14  
DQ13  
DQ10  
21 22 23 24 25 26 27 28 29 30 31 32 33  
VIEW OF PBGA PACKAGE BOTTOM  
Fully TTL Compatible  
10  
9
8
7
6
5
4
3
2
1
PIN NAMES  
A
B
C
D
E
D13  
V
D16 D17 D18 D20 D21 D23  
SS  
A0 – A11 . . . . . . . . . . . . . . . Address Inputs  
A12, X/Y . . . . . . . . . . Multiplexed Address  
V/S . . . . . . . . . Address Multiplexer Control  
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable  
E1, E2 . . . . . . . . . . . . . . . . . . . Chip Enable  
G . . . . . . . . . . . . . . . . . . . . . . Output Enable  
DQ0 – DQ23 . . . . . . . . . . Data Input/Output  
. . . . . . . . . . . . . . . +5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground  
NC . . . . . . . . . . . . . . . . . . . . No Connection  
W
D12 D14 D15  
E2  
D19  
V
D22 A5  
A3  
A4  
SS  
A2  
A0  
E1  
SS  
V
V
SS  
A1  
V
V
CC  
CC  
V
CC  
V
SS  
F
G
A6  
A8  
V/S NC  
G
A7  
A9  
X/Y  
A12  
For proper operation of the device, all V  
SS  
pins must be connected to ground.  
H
J
D11  
D9  
D8  
D7  
D4  
D5  
V
D1 A10 A11  
SS  
D10  
V
D6  
D3  
D2  
D0  
SS  
DSPRAM is a trademark of Motorola, Inc.  
Not to Scale  
REV 2  
4/95  
Motorola, Inc. 1995  
1234567...10

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