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MCM54800AJ10 PDF预览

MCM54800AJ10

更新时间: 2024-11-11 21:01:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
20页 509K
描述
Fast Page DRAM, 512KX8, 100ns, CMOS, PDSO28, 0.400 INCH, SOJ-28

MCM54800AJ10 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:0.400 INCH, SOJ-28Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.92访问模式:FAST PAGE
最长访问时间:100 ns其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O 类型:COMMONJESD-30 代码:R-PDSO-J28
JESD-609代码:e0长度:18.415 mm
内存密度:4194304 bit内存集成电路类型:FAST PAGE DRAM
内存宽度:8功能数量:1
端口数量:1端子数量:28
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ28,.44
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified刷新周期:1024
座面最大高度:3.75 mm自我刷新:NO
最大待机电流:0.001 A子类别:DRAMs
最大压摆率:0.08 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.16 mmBase Number Matches:1

MCM54800AJ10 数据手册

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Order this document  
by MCM54800A/D  
SEMICONDUCTOR  
TECHNICAL DATA  
MCM54800A  
MCM5L4800A  
MCM5V4800A  
512K x 8 CMOS Dynamic RAM  
Page Mode  
The MCM54800A is a 0.7µ CMOS high–speed, dynamic random access memory.  
It is organized as 524,288 eight–bit words and fabricated with CMOS silicon–gate  
process technology. Advanced circuit design and fine line processing provide high  
performance, improved reliability, and low cost.  
The MCM54800A requires only 10 address lines; row and column address inputs  
are multiplexed. The device is packaged in a standard 400 mil J–lead small outline  
package and a 400 mil thin small outline package (TSOP).  
J PACKAGE  
400 MIL SOJ  
CASE 810–03  
Three–State Data Output  
Fast Page Mode  
TTL–Compatible Inputs and Outputs  
RAS–Only Refresh  
CAS Before RAS Refresh  
Hidden Refresh  
Self Refresh (MCM5V4800A only)  
1024 Cycle Refresh:  
T PACKAGE  
400 MIL TSOP  
CASE 899–01  
PIN ASSIGNMENT  
MCM54800A = 16 ms  
MCM5L4800A and MCM5V4800A = 128 ms  
V
1
2
3
4
5
6
7
8
9
10  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
V
CC  
SS  
Fast Access Time (t ):  
RAC  
DQ0  
DQ1  
DQ2  
DQ7  
DQ6  
DQ5  
DQ4  
CAS  
G
MCM54800A–70, MCM5L4800A–70, and MCM5V4800A–70 = 70 ns (Max)  
MCM54800A–80, MCM5L4800A–80, and MCM5V4800A–80 = 80 ns (Max)  
MCM54800A–10, MCM5L4800A–10, and MCM5V4800A–10 = 100 ns (Max)  
Low Active Power Dissipation:  
DQ3  
NC  
MCM54800A–70, MCM5L4800A–70, and MCM5V4800A–70 = 578 mW (Max)  
MCM54800A–80, MCM5L4800A–80, and MCM5V4800A–80 = 495 mW (Max)  
MCM54800A–10, MCM5L4800A–10, and MCM5V4800A–10 = 440 mW (Max)  
Low Standby Power Dissipation:  
MCM54800A, MCM5L4800A, and MCM5V4800A = 11 mW (Max, TTL Levels)  
MCM54800A = 5.5 mW (Max, CMOS Levels)  
MCM54L800A and MCM5V4800A = 1.1 mW (Max, CMOS Levels)  
Battery Backup Power Dissipation:  
MCM5L4800A = 1.7 mW (Max, Battery Backup Mode, t  
Self Refresh Power Dissipation:  
W
RAS  
A9R  
A0  
NC  
A8  
A7  
A1  
11  
12  
18  
17  
A6  
= 125 µs)  
RC  
A2  
A5  
MCM5V4800A = 1.1 mW (Max, Self Refresh Mode)  
A4  
A3  
13  
14  
16  
15  
V
V
CC  
SS  
PIN NAMES  
A0 – A8, A9R . . . . . . . . . . Address Input  
RAS . . . . . . . . . . . . Row Address Strobe  
CAS . . . . . . . . . Column Address Strobe  
W . . . . . . . . . . . . . . . . . . . . . . . Write Input  
G . . . . . . . . . . . . . . . . . . . Output Enable  
DQ0 – DQ7 . . . . . . . . Data Input/Output  
Motorola is announcing the end–of–life status of the  
512Kx8 CMOS (MCM54800A) Dynamic RAM product  
family. Motorola will accept orders until April 3, 1996, and  
will support deliveries until October 3, 1996. There are no  
Motorola offerings that will directly replace these devices.  
V
CC  
V
SS  
. . . . . . . . . . . Power Supply (+ 5 V)  
. . . . . . . . . . . . . . . . . . . . . . . . Ground  
NC . . . . . . . . . . . . . . . . . . . . . No Connect  
REV 3  
10/95  
Motorola, Inc. 1995  

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