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MC74VHCT374A_06 PDF预览

MC74VHCT374A_06

更新时间: 2024-11-04 05:22:07
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安森美 - ONSEMI 触发器
页数 文件大小 规格书
7页 108K
描述
Octal D−Type Flip−Flop with 3−State Output

MC74VHCT374A_06 数据手册

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MC74VHCT374A  
Octal D−Type Flip−Flop  
with 3−State Output  
The MC74VHCT374A is an advanced high speed CMOS octal  
flip−flop with 3−state output fabricated with silicon gate CMOS  
technology. It achieves high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining CMOS low power  
dissipation.  
http://onsemi.com  
This 8−bit D−type flip−flop is controlled by a clock input and an  
output enable input. When the output enable input is high, the eight  
outputs are in a high impedance state.  
MARKING  
DIAGRAMS  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The VHCT inputs are compatible with TTL levels. This device can  
be used as a level converter for interfacing 3.3 V to 5.0 V, because it  
has full 5.0 V CMOS level output swings.  
The VHCT374A input and output (when disabled) structures  
provide protection when voltages between 0 V and 5.5 V are applied,  
regardless of the supply voltage. These input and output structures  
help prevent device destruction caused by supply  
voltage−input/output voltage mismatch, battery backup, hot insertion,  
etc.  
20  
1
VHCT374A  
AWLYYWWG  
SOIC−20WB  
SUFFIX DW  
CASE 751D  
1
20  
VHCT  
374A  
ALYWG  
G
1
TSSOP−20  
SUFFIX DT  
CASE 948E  
Features  
1
High Speed: f  
= 140 MHz (Typ) at V = 5.0 V  
CC  
max  
Low Power Dissipation: I = 4 mA (Max) at T = 25°C  
CC  
A
TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
20  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
74VHCT374  
AWLYWWG  
SOEIAJ−20  
SUFFIX M  
CASE 967  
Designed for 4.5 V to 5.5 V Operating Range  
1
1
Low Noise: V  
= 1.6 V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
A
= Assembly Location  
= Wafer Lot  
WL, L  
YY, Y  
ESD Performance:  
= Year  
Human Body Model > 2000 V;  
Machine Model > 200 V  
WW, W = Work Week  
= Pb−Free Package  
(Note: Microdot may be in either location)  
G or G  
Chip Complexity: 276 FETs or 69 Equivalent Gates  
Pb−Free Packages are Available*  
FUNCTION TABLE  
INPUTS  
CP  
OUTPUT  
Q
OE  
D
L
L
L
H
L
X
X
H
L
No Change  
Z
L, H,  
X
H
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
January, 2006 − Rev. 4  
MC74VHCT374A/D  

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