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MC74VHCT373AML2 PDF预览

MC74VHCT373AML2

更新时间: 2024-11-04 15:41:03
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 168K
描述
AHCT/VHCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, EIAJ, SOIC-20

MC74VHCT373AML2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.3
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.4
系列:AHCT/VHCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.575 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):14.5 ns认证状态:Not Qualified
座面最大高度:2.05 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.275 mm
Base Number Matches:1

MC74VHCT373AML2 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74VHCT373A is an advanced high speed CMOS octal latch with  
3–state output fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
This 8–bit D–type latch is controlled by a latch enable input and an output  
enable input. When the output enable input is high, the eight outputs are in a  
high impedance state.  
DW SUFFIX  
20–LEAD SOIC PACKAGE  
CASE 751D–04  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output.  
The VHCT inputs are compatible with TTL levels. This device can be used  
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS  
level output swings.  
The VHCT373A input and output (when disabled) structures provide  
protection when voltages between 0V and 5.5V are applied, regardless of  
the supply voltage. These input and output structures help prevent device  
destruction caused by supply voltage – input/output voltage mismatch,  
battery backup, hot insertion, etc.  
DT SUFFIX  
20–LEAD TSSOP PACKAGE  
CASE 948E–02  
High Speed: t  
= 7.7ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
M SUFFIX  
20–LEAD SOIC EIAJ PACKAGE  
CASE 967–01  
TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Designed for 4.5V to 5.5V Operating Range  
IL IH  
ORDERING INFORMATION  
MC74VHCTXXXADW  
MC74VHCTXXXADT  
MC74VHCTXXXAM  
SOIC  
TSSOP  
SOIC EIAJ  
Low Noise: V  
= 1.6V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 196 FETs or 49 Equivalent Gates  
PIN ASSIGNMENT  
1
20  
V
OE  
Q0  
D0  
D1  
CC  
LOGIC DIAGRAM  
2
3
4
19  
18  
17  
Q7  
D7  
D6  
2
5
3
D0  
D1  
D2  
D3  
D4  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
4
6
7
DATA  
INPUTS  
Q1  
Q2  
5
16  
15  
14  
13  
12  
11  
Q6  
Q5  
D5  
D4  
Q4  
8
9
NONINVERTING  
OUTPUTS  
13  
12  
15  
16  
19  
6
14  
17  
18  
D5  
D6  
D7  
D2  
7
D3  
8
Q3  
9
11  
1
GND  
10  
LE  
LE  
OE  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
OE  
LE  
D
L
L
L
H
H
L
H
L
X
X
H
L
No Change  
Z
H
X
6/97  
REV 0  
Motorola, Inc. 1997  

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