MC74LVX125
Quad Bus Buffer
With 5 V−Tolerant Inputs
The MC74LVX125 is an advanced high speed CMOS quad bus
buffer. The inputs tolerate voltages up to 7.0 V, allowing the interface
of 5.0 V systems to 3.0 V systems.
http://onsemi.com
The MC74LVX125 requires the 3−state control input (OE) to be set
High to place the output into the high impedance state.
Features
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
• High Speed: t = 4.4 ns (Typ) at V = 3.3 V
PD
CC
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
CC
A
• Power Down Protection Provided on Inputs
PIN ASSIGNMENT
• Balanced Propagation Delays
V
CC
OE3 D3 O3 OE2 D2 O2
• Low Noise: V
= 0.5 V (Max)
OLP
14 13 12 11 10
9
8
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance:
Human Body Model > 2000 V
Machine Model > 200 V
• These Devices are Pb−Free and are RoHS Compliant
1
2
3
4
5
6
7
OE0 D0 O0 OE1 D1 O1 GND
1
10
OE0
OE2
14−Lead (Top View)
2
4
3
6
9
8
D0
O0
O1
D2
O2
O3
MARKING DIAGRAMS
13
OE1
OE3
14
5
12
11
D1
D3
LVX125G
AWLYWW
Figure 1. Logic Diagram
Function
1
SOIC−14 NB
PIN NAMES
Pins
14
OEn
Dn
On
Output Enable Inputs
Data Inputs
3−State Outputs
LVX
125
ALYWG
G
1
FUNCTION TABLE
INPUTS
TSSOP−14
OUTPUTS
LVX125 = Specific Device Code
OEn
Dn
On
A
= Assembly Location
WL, L = Wafer Lot
= Year
L
L
H
L
H
X
L
H
Z
Y
WW, W = Work Week
G or G = Pb−Free Package
H = High Voltage Level; L = Low Voltage Level; Z = High Imped-
ance State; X = High or Low Voltage Level and Transitions Are
(Note: Microdot may be in either location)
Acceptable, for I reasons, DO NOT FLOAT Inputs
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
1
© Semiconductor Components Industries, LLC, 2014
Publication Order Number:
August, 2014 − Rev. 4
MC74LVX125/D