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MC74LVX126D PDF预览

MC74LVX126D

更新时间: 2024-11-11 05:22:11
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
5页 77K
描述
Quad Bus Buffe With 5V−Tolerant Inputs

MC74LVX126D 数据手册

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MC74LVX126  
Quad Bus Buffer  
With 5V−Tolerant Inputs  
The MC74LVX126 is an advanced high speed CMOS quad bus  
buffer. The inputs tolerate voltages up to 7.0 V, allowing the interface  
of 5.0 V systems to 3.0 V systems.  
The MC74LVX126 requires the 3−state control input (OE) to be set  
Low to place the output into the high impedance state.  
http://onsemi.com  
MARKING  
DIAGRAMS  
Features  
14  
High Speed: t = 4.4 ns (Typ) at V = 3.3 V  
PD  
CC  
SOIC−14  
D SUFFIX  
CASE 751A  
Low Power Dissipation: I = 4 mA (Max) at T = 25°C  
LVX126  
AWLYWW  
CC  
A
14  
Power Down Protection Provided on Inputs  
1
Balanced Propagation Delays  
1
Low Noise: V  
= 0.5 V (Max)  
OLP  
14  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
ESD Performance:  
Human Body Model >2000 V  
Machine Model >200 V  
LVX  
126  
ALYW  
TSSOP−14  
DT SUFFIX  
CASE 948G  
14  
1
1
14  
74LVX126  
ALYW  
SOEIAJ−14  
M SUFFIX  
CASE 965  
14  
1
1
A
= Assembly Location  
L, WL = Wafer Lot  
= Year  
W, WW = Work Week  
Y
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
February, 2005 − Rev. 2  
MC74LVX126/D  

MC74LVX126D 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV126ADR TI

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QUADRUPLE BUS BUFFER GATES WITH 3 STATE OUTPUTS
SN74LV126ADG4 TI

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QUADRUPLE BUS BUFFER GATES WITH 3 STATE OUTPUTS
SN74LV126AD TI

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QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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