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MC74LCX08SD PDF预览

MC74LCX08SD

更新时间: 2024-11-03 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
7页 139K
描述
LOW-VOLTAGE CMOS QUAD 2-INPUT AND GATE

MC74LCX08SD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:PLASTIC, SSOP-14
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.69Is Samacsys:N
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G14
JESD-609代码:e0长度:6.2 mm
逻辑集成电路类型:AND GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):225传播延迟(tpd):6.2 ns
认证状态:Not Qualified座面最大高度:2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

MC74LCX08SD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX08 is a high performance, quad 2–input AND gate  
operating from a 2.7 to 3.6V supply. High impedance TTL compatible  
inputs significantly reduce current loading to input drivers while TTL  
compatible outputs offer improved switching noise performance. A V  
specification of 5.5V allows MC74LCX08 inputs to be safely driven from  
5V devices.  
I
LOW–VOLTAGE CMOS  
QUAD 2–INPUT AND GATE  
Current drive capability is 24mA at the outputs.  
Designed for 2.7 to 3.6V V  
CC  
Operation  
5V Tolerant Inputs — Interface Capability With 5V TTL Logic  
LVTTL Compatible  
D SUFFIX  
PLASTIC SOIC  
CASE 751A–03  
LVCMOS Compatible  
14  
24mA Balanced Output Sink and Source Capability  
1
Near Zero Static Supply Current (10µA) Substantially Reduces System  
Power Requirements  
Latchup Performance Exceeds 500mA  
M SUFFIX  
PLASTIC SOIC EIAJ  
ESD Performance: Human Body Model >2000V; Machine Model >200V  
14  
CASE 965–01  
1
Pinout: 14–Lead (Top View)  
V
A2  
13  
B2  
12  
O2  
11  
A3  
10  
B3  
9
O3  
8
CC  
SD SUFFIX  
PLASTIC SSOP  
14  
14  
CASE 940A–03  
1
DT SUFFIX  
PLASTIC TSSOP  
14  
CASE 948G–01  
1
1
2
3
4
5
6
7
A0  
B0  
O0  
A1  
B1  
O1  
GND  
PIN NAMES  
LOGIC DIAGRAM  
1
Pins  
Function  
A0  
3
O0  
O1  
O2  
O3  
An, Bn  
On  
Data Inputs  
Outputs  
2
4
B0  
A1  
6
11  
8
5
B1  
A2  
FUNCTION TABLE  
INPUTS  
13  
OUTPUTS  
On  
12  
10  
B2  
A3  
An  
Bn  
L
L
H
H
L
H
L
L
L
L
9
B3  
H
H
11/96  
Motorola, Inc. 1996  
REV 1  
1

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