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MC74LCX125DT PDF预览

MC74LCX125DT

更新时间: 2024-11-03 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 146K
描述
LOW-VOLTAGE CMOS QUAD BUFFER

MC74LCX125DT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:LEAD FREE, TSSOP-14
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.04Is Samacsys:N
控制类型:ENABLE LOW系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:RAIL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:6 ns
传播延迟(tpd):7.2 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

MC74LCX125DT 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX125 is a high performance, non–inverting quad buffer  
operating from a 2.7 to 3.6V supply. High impedance TTL compatible  
inputs significantly reduce current loading to input drivers while TTL  
compatible outputs offer improved switching noise performance. A V  
I
LOW–VOLTAGE CMOS  
QUAD BUFFER  
specification of 5.5V allows MC74LCX125 inputs to be safely driven from  
5V devices. The MC74LCX125 is suitable for memory address driving  
and all TTL level bus oriented transceiver applications.  
Current drive capability is 24mA at the outputs. The Output Enable  
(OEn) inputs, when HIGH, disable the outputs by placing them in a HIGH  
Z condition.  
D SUFFIX  
PLASTIC SOIC  
CASE 751A–03  
Designed for 2.7 to 3.6V V  
CC  
5V Tolerant — Interface Capability With 5V TTL Logic  
Supports Live Insertion and Withdrawal  
Operation  
14  
1
I  
OFF  
LVTTL Compatible  
Specification Guarantees High Impedance When V  
= 0V  
CC  
M SUFFIX  
PLASTIC SOIC EIAJ  
CASE 965–01  
14  
LVCMOS Compatible  
1
24mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current in All Three Logic States (10µA)  
Substantially Reduces System Power Requirements  
SD SUFFIX  
PLASTIC SSOP  
CASE 940A–03  
14  
14  
Latchup Performance Exceeds 500mA  
1
1
ESD Performance: Human Body Model >2000V; Machine Model >200V  
DT SUFFIX  
PLASTIC TSSOP  
CASE 948G–01  
Pinout: 14–Lead (Top View)  
V
OE3  
13  
D3  
12  
O3  
11  
OE2  
10  
D2  
9
O2  
8
CC  
14  
PIN NAMES  
Pins  
Function  
OEn  
Dn  
On  
Output Enable Inputs  
Data Inputs  
3–State Outputs  
1
2
3
4
5
6
7
OE0  
D0  
O0  
OE1  
D1  
O1  
GND  
FUNCTION TABLE  
INPUTS  
LOGIC DIAGRAM  
OUTPUTS  
On  
1
10  
OE0  
OE2  
OEn  
Dn  
2
4
3
9
8
L
L
H
L
H
X
L
H
Z
D0  
O0  
O1  
D2  
O2  
O3  
13  
OE1  
OE3  
5
6
12  
11  
H = High Voltage Level; L = Low VoltageLevel;Z=HighImped-  
ance State; X = High or Low Voltage Level and Transitions Are  
D1  
D3  
Acceptable, for I  
reasons, DO NOT FLOAT Inputs  
CC  
11/96  
Motorola, Inc. 1996  
REV 1  
1

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