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MC74HCT573ADW PDF预览

MC74HCT573ADW

更新时间: 2024-11-22 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器
页数 文件大小 规格书
6页 206K
描述
Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs

MC74HCT573ADW 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SOP,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.79
其他特性:BROADSIDE VERSION OF 373系列:HCT
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):45 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.5 mm

MC74HCT573ADW 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
20  
High–Performance Silicon–Gate CMOS  
1
The MC74HCT573A is identical in pinout to the LS573. This device may  
be used as a level converter for interfacing TTL or NMOS outputs to  
High–Speed CMOS inputs.  
These latches appear transparent to data (i.e., the outputs change  
asynchronously) when Latch Enable is high. When Latch Enable goes low,  
data meeting the setup and hold times becomes latched.  
The Output Enable input does not affect the state of the latches, but when  
Output Enable is high, all device outputs are forced to the high–impedance  
state. Thus, data may be latched even when the outputs are not enabled.  
The HCT573A is identical in function to the HCT373A but has the Data  
Inputs on the opposite side of the package from the outputs to facilitate PC  
board layout.  
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948E–02  
20  
1
ORDERING INFORMATION  
MC74HCTXXXAN Plastic  
MC74HCTXXXADW SOIC  
MC74HCTXXXADT TSSOP  
The HCT573A is the noninverting version of the HC563A.  
Output Drive Capability: 15 LSTTL Loads  
TTL/NMOS–Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 10 µA  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: 234 FETs or 58.5 Equivalent Gates  
PIN ASSIGNMENT  
OUTPUT  
ENABLE  
1
20  
V
CC  
D0  
2
3
4
19  
18  
17  
Q0  
Q1  
Q2  
D1  
D2  
— Improved Propagation Delays  
— 50% Lower Quiescent Power  
D3  
D4  
D5  
D6  
5
6
7
8
16  
15  
14  
13  
Q3  
Q4  
Q5  
Q6  
LOGIC DIAGRAM  
2
3
4
19  
18  
17  
D7  
9
12  
11  
Q7  
D0  
D1  
D2  
Q0  
Q1  
Q2  
LATCH  
ENABLE  
GND  
10  
5
6
16  
15  
NONINVERTING  
OUTPUTS  
DATA  
INPUTS  
D3  
D4  
Q3  
Q4  
FUNCTION TABLE  
7
8
14  
13  
D5  
D6  
D7  
Q5  
Q6  
Q7  
Inputs  
Output  
9
12  
Output Latch  
Enable Enable  
D
Q
11  
1
L
L
L
H
H
L
H
L
X
X
H
LATCH ENABLE  
L
No Change  
Z
PIN 20 = V  
PIN 10 = GND  
CC  
OUTPUT ENABLE  
H
X
X = Don’t Care  
Z = High Impedance  
Design Criteria  
Internal Gate Count*  
Value  
58.5  
1.5  
Units  
ea  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
Speed Power Product  
ns  
5.0  
µW  
pJ  
0.0075  
* Equivalent to a two–input NAND gate.  
10/96  
REV 7  
Motorola, Inc. 1996  

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