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MC74HCT573ADWR2 PDF预览

MC74HCT573ADWR2

更新时间: 2024-11-25 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 189K
描述
Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs

MC74HCT573ADWR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:7.07Is Samacsys:N
系列:HCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):235电源:5 V
Prop。Delay @ Nom-Sup:45 ns传播延迟(tpd):45 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn80Pb20)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

MC74HCT573ADWR2 数据手册

 浏览型号MC74HCT573ADWR2的Datasheet PDF文件第2页浏览型号MC74HCT573ADWR2的Datasheet PDF文件第3页浏览型号MC74HCT573ADWR2的Datasheet PDF文件第4页浏览型号MC74HCT573ADWR2的Datasheet PDF文件第5页浏览型号MC74HCT573ADWR2的Datasheet PDF文件第6页浏览型号MC74HCT573ADWR2的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
http://onsemi.com  
The MC74HCT573A is identical in pinout to the LS573. This  
device may be used as a level converter for interfacing TTL or NMOS  
outputs to High–Speed CMOS inputs.  
MARKING  
DIAGRAMS  
20  
These latches appear transparent to data (i.e., the outputs change  
asynchronously) when Latch Enable is high. When Latch Enable goes  
low, data meeting the setup and hold times becomes latched.  
The Output Enable input does not affect the state of the latches, but  
when Output Enable is high, all device outputs are forced to the  
high–impedance state. Thus, data may be latched even when the  
outputs are not enabled.  
The HCT573A is identical in function to the HCT373A but has the  
Data Inputs on the opposite side of the package from the outputs to  
facilitate PC board layout.  
PDIP–20  
N SUFFIX  
CASE 738  
MC74HCT573AN  
AWLYYWW  
20  
1
1
20  
SOIC WIDE–20  
DW SUFFIX  
CASE 751D  
HCT573A  
AWLYYWW  
20  
1
1
20  
Output Drive Capability: 15 LSTTL Loads  
TTL/NMOS–Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 10 µA  
HCT  
573A  
ALYW  
TSSOP–20  
DT SUFFIX  
CASE 948G  
20  
1
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
In Compliance with the Requirements Defined by JEDEC Standard  
WW = Work Week  
No. 7A  
Chip Complexity: 234 FETs or 58.5 Equivalent Gates  
— Improved Propagation Delays  
ORDERING INFORMATION  
— 50% Lower Quiescent Power  
Device  
Package  
PDIP–20  
Shipping  
1440 / Box  
38 / Rail  
MC74HCT573AN  
MC74HCT573ADW  
SOIC–WIDE  
MC74HCT573ADWR2 SOIC–WIDE 1000 / Reel  
MC74HCT573ADT  
TSSOP–20  
75 / Rail  
MC74HCT573ADTR2  
TSSOP–20 2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 8  
MC74HCT573A/D  

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