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MC74HC589N PDF预览

MC74HC589N

更新时间: 2024-11-16 11:07:51
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 262K
描述
8-Bit Serial or Parallel-Input/Serial-Output Shift Register with 3-State Output High-Performance Silicon-Gate CMOS

MC74HC589N 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
High–Performance Silicon–Gate CMOS  
16  
1
The MC54/74HC589 is similar in function to the HC597, which is not a  
3–state device. The device inputs are compatible with standard CMOS  
outputs, with pullup resistors, they are compatible with LSTTL outputs.  
This device consists of an 8–bit storage latch which feeds parallel data to  
an 8–bit shift register. Data can also be loaded serially (see Function Table).  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
The shift register output, Q , is a three–state output, allowing this device to  
H
1
be used in bus–oriented systems.  
The HC589 directly interfaces with the Motorola SPI serial data port on  
CMOS MPUs and MCUs.  
D SUFFIX  
16  
SOIC PACKAGE  
CASE 751B–05  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
1
Low Input Current: 1 µA  
ORDERING INFORMATION  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXD  
Ceramic  
Plastic  
SOIC  
Chip Complexity: 526 FETs or 131.5 Equivalent Gates  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
B
C
1
2
16  
15  
V
A
CC  
SERIAL  
14  
DATA  
S
A
D
E
F
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
S
A
INPUT  
SERIAL SHIFT/  
PARALLEL LOAD  
15  
LATCH CLOCK  
A
B
1
2
3
4
5
G
H
SHIFT CLOCK  
C
V
= PIN 16  
OUTPUT ENABLE  
CC  
GND = PIN 8  
PARALLEL  
DATA  
INPUTS  
D
E
F
GND  
Q
H
DATA  
LATCH  
SHIFT  
REGISTER  
6
7
G
SERIAL  
DATA  
OUTPUT  
9
H
Q
H
12  
LATCH CLOCK  
11  
13  
10  
SHIFT CLOCK  
SERIAL SHIFT/  
PARALLEL LOAD  
OUTPUT ENABLE  
10/95  
Motorola, Inc. 1995  
REV 6  

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