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MC74HC595ADTEL

更新时间： 2024-09-23 13:11:19
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
12页 252K
描述
IC,SHIFT REGISTER,HC-CMOS,TSSOP,16PIN,PLASTIC

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中文翻译

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MC74HC595ADTEL 技术参数

是否Rohs认证：不符合生命周期：Obsolete
Reach Compliance Code：not_compliant风险等级：5.92
Is Samacsys：N计数方向：RIGHT
JESD-30 代码：R-PDSO-G16JESD-609代码：e0
最大频率@ Nom-Sup：20000000 Hz位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：2/6 V
认证状态：Not Qualified子类别：Shift Registers
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUALBase Number Matches：1

MC74HC595ADTEL 数据手册

 浏览型号MC74HC595ADTEL的Datasheet PDF文件第2页浏览型号MC74HC595ADTEL的Datasheet PDF文件第3页浏览型号MC74HC595ADTEL的Datasheet PDF文件第4页浏览型号MC74HC595ADTEL的Datasheet PDF文件第5页浏览型号MC74HC595ADTEL的Datasheet PDF文件第6页浏览型号MC74HC595ADTEL的Datasheet PDF文件第7页 
http://onsemi.com  
High–Performance Silicon–Gate CMOS  
MARKING  
DIAGRAMS  
16  
The MC74HC595A consists of an 8–bit shift register and an 8–bit  
D–type latch with three–state parallel outputs. The shift register  
accepts serial data and provides a serial output. The shift register also  
provides parallel data to the 8–bit latch. The shift register and latch  
have independent clock inputs. This device also has an asynchronous  
reset for the shift register.  
PDIP–16  
N SUFFIX  
CASE 648  
MC74HC595AN  
AWLYYWW  
16  
16  
1
1
The HC595A directly interfaces with the SPI serial data port on  
CMOS MPUs and MCUs.  
16  
SO–16  
D SUFFIX  
CASE 751B  
HC595A  
AWLYWW  
• Output Drive Capability: 15 LSTTL Loads  
• Outputs Directly Interface to CMOS, NMOS, and TTL  
• Operating Voltage Range: 2.0 to 6.0 V  
1
1
16  
• Low Input Current: 1.0 µA  
• High Noise Immunity Characteristic of CMOS Devices  
• In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
HC  
595A  
ALYW  
TSSOP–16  
DT SUFFIX  
CASE 948F  
16  
1
1
• Chip Complexity: 328 FETs or 82 Equivalent Gates  
• Improvements over HC595  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
— Improved Propagation Delays  
— 50% Lower Quiescent Power  
— Improved Input Noise and Latchup Immunity  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
Q
1
2
3
4
5
6
7
8
16  
15  
14  
V
CC  
B
SERIAL  
DATA  
INPUT  
14  
15  
1
Q
C
Q
A
A
Q
A
Q
B
Q
D
A
2
3
4
5
6
7
Q
C
Q
E
13 OUTPUT ENABLE  
12 LATCH CLOCK  
11 SHIFT CLOCK  
10 RESET  
PARALLEL  
DATA  
OUTPUTS  
Q
D
Q
E
Q
F
SHIFT  
Q
G
LATCH  
REGISTER  
Q
F
Q
H
Q
G
GND  
9
SQ  
H
Q
H
SHIFT  
CLOCK  
11  
10  
12  
13  
SERIAL  
DATA  
OUTPUT  
9
RESET  
SQ  
H
ORDERING INFORMATION  
LATCH  
CLOCK  
Device  
Package  
PDIP–16  
SOIC–16  
SOIC–16  
TSSOP–16  
Shipping  
V
= PIN 16  
CC  
GND = PIN 8  
OUTPUT  
ENABLE  
MC74HC595AN  
2000 / Box  
48 / Rail  
MC74HC595AD  
MC74HC595ADR2  
MC74HC595ADT  
MC74HC595ADTR2  
2500 / Reel  
96 / Rail  
TSSOP–16 2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 8  
MC74HC595A/D  
1234567...12

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