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MC74HC595ADT PDF预览

MC74HC595ADT

更新时间: 2024-09-22 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 227K
描述
8-Bit Serial-Input/Serial or Parallel-Output Shift Register with 3-State Outputs

MC74HC595ADT 技术参数

生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.42其他特性:PARALLEL OUTPUT IS REGISTERED; UNREGISTERED SERIAL SHIFT RIGHT OUTPUT
计数方向:RIGHT系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:SERIAL IN PARALLEL OUT位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):42 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:20 MHz
Base Number Matches:1

MC74HC595ADT 数据手册

 浏览型号MC74HC595ADT的Datasheet PDF文件第2页浏览型号MC74HC595ADT的Datasheet PDF文件第3页浏览型号MC74HC595ADT的Datasheet PDF文件第4页浏览型号MC74HC595ADT的Datasheet PDF文件第5页浏览型号MC74HC595ADT的Datasheet PDF文件第6页浏览型号MC74HC595ADT的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
High–Performance Silicon–Gate CMOS  
16  
1
The MC54/74HC595A is identical in pinout to the LS595. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
The HC595A consists of an 8–bit shift register and an 8–bit D–type latch  
with three–state parallel outputs. The shift register accepts serial data and  
provides a serial output. The shift register also provides parallel data to the  
8–bit latch. The shift register and latch have independent clock inputs. This  
device also has an asynchronous reset for the shift register.  
The HC595A directly interfaces with the Motorola SPI serial data port on  
CMOS MPUs and MCUs.  
16  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
16  
1
ORDERING INFORMATION  
Chip Complexity: 328 FETs or 82 Equivalent Gates  
Improvements over HC595  
— Improved Propagation Delays  
— 50% Lower Quiescent Power  
— Improved Input Noise and Latchup Immunity  
MC54HCXXXAJ  
Ceramic  
Plastic  
SOIC  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
TSSOP  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
Q
1
2
16  
15  
V
CC  
SERIAL  
DATA  
INPUT  
B
C
D
14  
15  
1
A
Q
Q
A
B
Q
Q
Q
A
A
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
2
3
4
5
Q
C
Q
OUTPUT ENABLE  
LATCH CLOCK  
SHIFT CLOCK  
RESET  
E
PARALLEL  
DATA  
OUTPUTS  
Q
Q
Q
Q
Q
D
E
F
Q
Q
F
SHIFT  
REGISTER  
LATCH  
G
6
7
Q
H
G
H
GND  
SQ  
H
SHIFT  
CLOCK  
11  
10  
12  
13  
SERIAL  
DATA  
9
RESET  
SQ  
H
OUTPUT  
LATCH  
CLOCK  
OUTPUT  
ENABLE  
V
= PIN 16  
CC  
GND = PIN 8  
3/97  
REV 7  
Motorola, Inc. 1997  

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