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MC74HC4060AD PDF预览

MC74HC4060AD

更新时间: 2024-09-14 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 振荡器计数器触发器逻辑集成电路光电二极管输出元件输入元件
页数 文件大小 规格书
12页 208K
描述
14-Stage Binary Ripple Counter With Oscillator

MC74HC4060AD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:7.71
其他特性:OUTPUTS FROM 10 STAGES AVAILABLE计数方向:UP
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:25000000 Hz
最大I(ol):0.004 A工作模式:ASYNCHRONOUS
湿度敏感等级:1位数:14
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:RAIL
峰值回流温度(摄氏度):240电源:2/6 V
传播延迟(tpd):1000 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Counters
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:NEGATIVE EDGE
宽度:3.9 mm最小 fmax:40 MHz
Base Number Matches:1

MC74HC4060AD 数据手册

 浏览型号MC74HC4060AD的Datasheet PDF文件第2页浏览型号MC74HC4060AD的Datasheet PDF文件第3页浏览型号MC74HC4060AD的Datasheet PDF文件第4页浏览型号MC74HC4060AD的Datasheet PDF文件第5页浏览型号MC74HC4060AD的Datasheet PDF文件第6页浏览型号MC74HC4060AD的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74C4060A is identical in pinout to the standard CMOS  
MC14060B. The device inputs are compatible with standard CMOS  
outputs; with pullup resistors, they are compatible with LSTTL  
outputs.  
This device consists of 14 master–slave flip–flops and an oscillator  
with a frequency that is controlled either by a crystal or by an RC  
circuit connected externally. The output of each flip–flop feeds the  
next and the frequency at each output is half of that of the preceding  
one. The state of the counter advances on the negative–going edge of  
the Osc In. The active–high Reset is asynchronous and disables the  
oscillator to allow very low power consumption during stand–by  
operation.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP–16  
N SUFFIX  
CASE 648  
MC74HC4060AN  
AWLYYWW  
16  
16  
1
1
16  
SO–16  
D SUFFIX  
CASE 751B  
HC4060A  
AWLYWW  
State changes of the Q outputs do not occur simultaneously because  
of internal ripple delays. Therefore, decoded output signals are subject  
to decoding spikes and may have to be gated with Osc Out 2 of the  
HC4060A.  
1
1
16  
HC40  
60A  
ALYW  
TSSOP–16  
DT SUFFIX  
CASE 948F  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
16  
1
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With JEDEC Standard No. 7A Requirements  
Chip Complexity: 390 FETs or 97.5 Equivalent Gates  
WW = Work Week  
LOGIC DIAGRAM  
Osc Out 1 Osc Out 2  
10  
9
Pinout: 16–Lead Plastic Package (Top View)  
Osc Osc  
Out 1 Out 2  
Q9 Reset Osc In  
7
5
4
Q4  
Q5  
Q6  
Q7  
Q8  
Q9  
Q10  
Q12  
Q13  
Q14  
V
Q10 Q8  
15 14  
CC  
16  
13  
12  
11  
10  
9
11  
Osc In  
6
14  
13  
15  
1
2
3
1
2
3
4
5
6
7
8
GND  
Q12 Q13 Q14 Q6  
Q5  
Q7  
Q4  
12  
Pin 16 = V  
CC  
Pin 8 = GND  
Reset  
FUNCTION TABLE  
Clock  
Reset  
Output State  
L
L
No Charge  
ORDERING INFORMATION  
Advance to Next State  
All Outputs Are Low  
Device  
Package  
PDIP–16  
SOIC–16  
SOIC–16  
TSSOP–16  
Shipping  
X
H
MC74HC4060AN  
MC74HC4060AD  
MC74HC4060ADR2  
MC74HC4060ADT  
MC74HC4060ADTR2  
2000 / Box  
48 / Rail  
2500 / Reel  
96 / Rail  
TSSOP–16 2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 2  
MC74HC4060A/D  

MC74HC4060AD 替代型号

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