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MC74HC299

更新时间： 2024-11-02 05:09:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
8页 124K
描述
8-Bit Bidirectional Universal Shift Register with Parallel I/O

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中文翻译

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MC74HC299 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
The MC74HC299 is identical in pinout to the LS299. The device inputs are  
compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
20  
1
The HC299 features a multiplexed parallel input/output data port to  
achieve full 8–bit handling in a 20 pin package. Due to the large output drive  
capability and the 3–state feature, this device is ideally suited for interface  
with bus lines in a bus–oriented system.  
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
Two Mode–Select inputs and two Output Enable inputs are used to  
choose the mode of operation as listed in the Function Table. Synchronous  
ORDERING INFORMATION  
MC74HCXXXN  
Plastic  
SOIC  
parallel loading is accomplished by taking both Mode–Select lines, S and  
1
MC74HCXXXDW  
S , high. This places the outputs in the high–impedance state, which permits  
2
data applied to the data port to be clocked into the register. Reading out of  
the register can be accomplished when the outputs are enabled. The  
active–low asynchronous Reset overrides all other inputs.  
PIN ASSIGNMENT  
•
Output Drive Capability: 15 LSTTL Loads for Q through Q  
A
H
S1  
1
20  
V
10 LSTTL Loads for Q ′ and Q ′  
CC  
A
H
•
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
OE1  
OE2  
2
3
19  
18  
S2  
S
H
P
Q
4
17  
Q ′  
H
G/  
G
P
Q
5
16  
15  
14  
13  
12  
11  
P
/Q  
E/  
E
H
H
P
/Q  
6
P /Q  
F
C
C
F
•
Chip Complexity: 398 FETs or 99.5 Equivalent Gates  
P /Q  
7
P /Q  
D
A
A
D
Q
′
8
P /Q  
B
A
B
RESET  
GND  
9
CLOCK  
LOGIC DIAGRAM  
10  
S
A
7
13  
6
14  
5
15  
4
16  
8
17  
P /Q  
A
A
B
C
D
E
F
P
P
P
P
/Q  
/Q  
/Q  
B
C
D
3–STATE  
PARALLEL DATA PORT  
(INPUTS/OUTPUTS)  
11  
18  
SERIAL  
DATA  
INPUTS  
S
(SHIFT RIGHT)  
(SHIFT LEFT)  
A
/Q  
E
S
P /Q  
H
F
P
P
Q
Q
/Q  
/Q  
G
H
G
H
12  
CLOCK  
RESET  
SERIAL DATA  
OUTPUTS  
A′  
H′  
9
1
19  
2
MODE  
S
S
1
2
SELECT  
PIN 20 = V  
CC  
PIN 10 = GND  
OUTPUT OE1  
ENABLES OE2  
3
10/95  
Motorola, Inc. 1995  
REV 6  
12345678

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与MC74HC299相关器件

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MC74HC299D MOTOROLA

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 		Shift Register, 8-Bit, CMOS, PDSO20
MC74HC299DW MOTOROLA

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 		8-Bit Bidirectional Universal Shift Register with Parallel I/O
MC74HC299DWD MOTOROLA

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 		HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PD
MC74HC299DWDS MOTOROLA

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 		Shift Register, 8-Bit, CMOS, PDSO20
MC74HC299DWR2 MOTOROLA

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 		HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PD
MC74HC299DWS MOTOROLA

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 		Shift Register, 8-Bit, CMOS, PDSO20
MC74HC299N MOTOROLA

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 		8-Bit Bidirectional Universal Shift Register with Parallel I/O
MC74HC299ND MOTOROLA

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 		Parallel In Parallel Out, HC/UH Series, 8-Bit, Bidirectional, True Output, CMOS, PDIP20, 7
MC74HC299NS MOTOROLA

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 		Shift Register, 8-Bit, CMOS, PDIP20
MC74HC30 MOTOROLA

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 		8-Input NAND Gate High-Performance Silicon-Gate CMOS

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