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MC74HC280DDS

更新时间： 2024-11-02 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
6页 208K
描述
Parity Generator/Checker, CMOS, PDSO14

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中文翻译

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MC74HC280DDS 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：SOP, SOP14,.25Reach Compliance Code：unknown
风险等级：5.92Is Samacsys：N
JESD-30 代码：R-PDSO-G14JESD-609代码：e0
逻辑集成电路类型：PARITY GENERATOR/CHECKER端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：2/6 V
子类别：Arithmetic Circuits表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
Base Number Matches：1

MC74HC280DDS 数据手册

 浏览型号MC74HC280DDS的Datasheet PDF文件第2页浏览型号MC74HC280DDS的Datasheet PDF文件第3页浏览型号MC74HC280DDS的Datasheet PDF文件第4页浏览型号MC74HC280DDS的Datasheet PDF文件第5页浏览型号MC74HC280DDS的Datasheet PDF文件第6页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
N SUFFIX  
PLASTIC PACKAGE  
CASE 646–06  
14  
The MC74HC280 is identical in pinout to the LS280. The device inputs are  
compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
1
This circuit consists of 9 data–bit inputs (A through I) and 2 outputs (Even  
Parity and Odd Parity) to allow both odd and even parity applications. Words  
greater than 9–bits can be accommodated by cascading other HC280  
devices.  
D SUFFIX  
SOIC PACKAGE  
CASE 751A–03  
14  
1
This device can be used in systems utilizing the LS180 parity generator/  
checker. Although the HC280 does not have expander inputs, the  
corresponding function is provided by an input at pin 4 and the absence of  
any connection at pin 3. This permits the HC280 to be substituted for the  
LS180 to produce a similar function, even if the HC280s are mixed with  
existing LS180s. NOTE: Pullup resistors must be used on the LS180 outputs  
to interface with the HC280.  
ORDERING INFORMATION  
MC74HCXXXN  
MC74HCXXXD  
Plastic  
SOIC  
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
PIN ASSIGNMENT  
G
H
1
2
3
4
14  
13  
12  
11  
V
F
E
CC  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
NC  
I
D
•
Chip Complexity: 226 FETs or 56.5 Equivalent Gates  
EVEN PARITY  
ODD PARITY  
5
6
10  
9
C
B
LOGIC DIAGRAM  
GND  
7
8
A
NC = NO CONNECTION  
8
A
9
B
10  
C
FUNCTION TABLE  
9–BIT  
DATA–  
WORD  
INPUTS  
11  
D
E
F
G
H
I
5
6
Outputs  
EVEN PARITY  
ODD PARITY  
PARITY  
OUTPUTS  
12  
13  
1
Number of Inputs A through  
I That are High  
Even  
Parity  
Odd  
Parity  
0, 2, 4, 6, 8  
1, 3, 5, 7, 9  
H
L
L
2
H
4
V
= PIN 14  
CC  
GND = PIN 7  
NO CONNECTION = PIN 3  
10/95  
Motorola, Inc. 1995  
REV 6  
123456

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