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MC74HC164NS

更新时间: 2024-10-30 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
7页 207K
描述
Shift Register, 8-Bit, CMOS, PDIP14

MC74HC164NS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-PDIP-T14
JESD-609代码:e0位数:8
功能数量:1端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:2/6 V
认证状态:Not Qualified子类别:Shift Registers
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC74HC164NS 数据手册

 浏览型号MC74HC164NS的Datasheet PDF文件第2页浏览型号MC74HC164NS的Datasheet PDF文件第3页浏览型号MC74HC164NS的Datasheet PDF文件第4页浏览型号MC74HC164NS的Datasheet PDF文件第5页浏览型号MC74HC164NS的Datasheet PDF文件第6页浏览型号MC74HC164NS的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
Do Not Use for New Designs  
High–Performance Silicon–Gate CMOS  
THIS DEVICE WILL BE SUPERCEDED  
BY MC54/74HC164A IN THE  
The MC54/74HC164 is identical in pinout to the LS164. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
SECOND QUARTER OF 1996  
The MC54/74HC164 is an 8–bit, serial–input to parallel–output shift  
register. Two serial data inputs, A1 and A2, are provided so that one input  
may be used as a data enable. Data is entered on each rising edge of the  
clock. The active–low asynchronous Reset overrides the Clock and Serial  
Data inputs.  
J SUFFIX  
CERAMIC PACKAGE  
14  
CASE 632–08  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
N SUFFIX  
PLASTIC PACKAGE  
14  
CASE 646–06  
Low Input Current: 1 µA  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
D SUFFIX  
SOIC PACKAGE  
CASE 751A–03  
14  
Chip Complexity: 244 FETs or 61 Equivalent Gates  
1
ORDERING INFORMATION  
LOGIC DIAGRAM  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXD  
Ceramic  
Plastic  
SOIC  
1
SERIAL  
DATA  
INPUTS  
3
4
A1  
A2  
Q
Q
A
B
C
D
E
F
DATA  
2
5
PIN ASSIGNMENT  
Q
Q
Q
Q
Q
Q
6
PARALLEL  
DATA  
OUTPUTS  
A1  
A2  
1
2
3
4
14  
13  
12  
11  
V
CC  
10  
11  
12  
13  
Q
Q
Q
Q
H
G
F
Q
A
Q
B
G
H
8
9
CLOCK  
RESET  
Q
Q
5
6
10  
9
C
E
RESET  
CLOCK  
D
GND  
7
8
PIN 14 = V  
CC  
PIN 7 = GND  
FUNCTION TABLE  
Inputs  
Reset Clock A1 A2  
Outputs  
Q  
H
Q
Q
B
A
L
H
H
H
X
X
X
H
D
X
X
D
H
L
L
L
No Change  
D
D
Q
Q
Q  
Q  
An  
An  
Gn  
Gn  
D = data input  
– Q = data shifted from the preceding  
Q
An  
Gn  
stage on a rising edge at the clock input.  
10/95  
REV 7  
Motorola, Inc. 1995  

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