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MC74HC165AN PDF预览

MC74HC165AN

更新时间: 2024-11-26 23:05:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 283K
描述
8-Bit Serial or Parallel-Input/Serial-Output Shift Register

MC74HC165AN 技术参数

生命周期:Transferred零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.56Is Samacsys:N
其他特性:CLOCK INHIBIT计数方向:RIGHT
系列:HC/UHJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.175 mm
负载电容(CL):50 pF逻辑集成电路类型:PARALLEL IN SERIAL OUT
最大频率@ Nom-Sup:12000000 Hz位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:2/6 V传播延迟(tpd):32 ns
认证状态:Not Qualified座面最大高度:4.44 mm
子类别:Shift Registers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:25 MHz
Base Number Matches:1

MC74HC165AN 数据手册

 浏览型号MC74HC165AN的Datasheet PDF文件第2页浏览型号MC74HC165AN的Datasheet PDF文件第3页浏览型号MC74HC165AN的Datasheet PDF文件第4页浏览型号MC74HC165AN的Datasheet PDF文件第5页浏览型号MC74HC165AN的Datasheet PDF文件第6页浏览型号MC74HC165AN的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
High–Performance Silicon–Gate CMOS  
The MC54/74HC165A is identical in pinout to the LS165. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
This device is an 8–bit shift register with complementary outputs from the  
last stage. Data may be loaded into the register either in parallel or in serial  
form. When the Serial Shift/Parallel Load input is low, the data is loaded  
asynchronously in parallel. When the Serial Shift/Parallel Load input is high,  
the data is loaded serially on the rising edge of either Clock or Clock Inhibit  
(see the Function Table).  
The 2–input NOR clock may be used either by combining two independent  
clock sources or by designating one of the clock inputs to act as a clock  
inhibit.  
16  
16  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
16  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
1
Low Input Current: 1 µA  
ORDERING INFORMATION  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
MC54HCXXXAJ  
Ceramic  
Plastic  
SOIC  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
Chip Complexity: 286 FETs or 71.5 Equivalent Gates  
TSSOP  
LOGIC DIAGRAM  
11  
A
12  
PIN ASSIGNMENT  
B
9
7
13  
Q
Q
SERIAL SHIFT/  
H
SERIAL  
DATA  
OUTPUTS  
C
D
E
1
2
16  
15  
V
CC  
PARALLEL LOAD  
PARALLEL  
DATA  
INPUTS  
14  
3
CLOCK  
CLOCK INHIBIT  
H
E
F
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
D
C
B
A
4
5
F
G
H
G
H
6
PIN 16 = V  
CC  
PIN 8 = GND  
SERIAL  
DATA  
INPUT  
10  
S
A
Q
S
A
H
1
SERIAL SHIFT/  
PARALLEL LOAD  
GND  
Q
H
2
CLOCK  
15  
CLOCK INHIBIT  
FUNCTION TABLE  
Inputs  
Internal Stages  
Output  
Serial Shift/  
Clock  
Parallel Load  
Inhibit  
Clock  
S
A
A – H  
Q
Q
Q
H
Operation  
A
B
L
X
X
X
a h  
a
b
h
Asynchronous Parallel Load  
H
H
L
L
L
H
X
X
L
H
Q
Q
Q
Q
An  
An  
Gn  
Gn  
Serial Shift via Clock  
H
H
L
L
L
H
X
X
L
H
Q
Q
Q
Q
An  
An  
Gn  
Gn  
Serial Shift via Clock Inhibit  
H
H
X
H
H
X
X
X
X
X
No Change  
Inhibited Clock  
No Clock  
H
L
L
X
X
No Change  
X = don’t care  
Q
– Q  
= Data shifted from the preceding stage  
Gn  
An  
This document contains information on a product under development. Motorola reserves the right to change or  
discontinue this product without notice.  
10/95  
REV 0  
Motorola, Inc. 1995  

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