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MC74HC165

更新时间： 2024-10-29 23:05:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
8页 239K
描述
8-Bit Serial or Parallel-Input/Serial-Output Shift Register

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MC74HC165 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
The MC54/74HC165 is identical in pinout to the LS165. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
16  
1
This device is an 8–bit shift register with complementary outputs from the  
last stage. Data may be loaded into the register either in parallel or in serial  
form. When the Serial Shift/Parallel Load input is low, the data is loaded  
asynchronously in parallel. When the Serial Shift/Parallel Load input is high,  
the data is loaded serially on the rising edge of either Clock or Clock Inhibit  
(see the Function Table).  
The 2–input NOR clock may be used either by combining two independent  
clock sources or by designating one of the clock inputs to act as a clock  
inhibit.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
1
D SUFFIX  
16  
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
SOIC PACKAGE  
CASE 751B–05  
1
Low Input Current: 1 µA  
ORDERING INFORMATION  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXD  
Ceramic  
Plastic  
SOIC  
•
Chip Complexity: 286 FETs or 71.5 Equivalent Gates  
LOGIC DIAGRAM  
11  
A
PIN ASSIGNMENT  
12  
B
SERIAL SHIFT/  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CC  
9
7
13  
PARALLEL LOAD  
Q
Q
H
SERIAL  
DATA  
OUTPUTS  
C
D
E
CLOCK  
CLOCK INHIBIT  
PARALLEL  
DATA  
INPUTS  
14  
3
E
F
D
C
B
A
H
4
5
F
G
H
G
H
6
PIN 16 = V  
PIN 8 = GND  
SERIAL  
DATA  
INPUT  
CC  
10  
Q
H
S
A
S
A
GND  
Q
H
1
SERIAL SHIFT/PARALLEL LOAD  
2
CLOCK  
15  
CLOCK INHIBIT  
FUNCTION TABLE  
Inputs  
Clock  
Internal Stages  
Output  
Serial Shift/  
Parallel Load  
Inhibit  
Clock  
S
A
A – H  
Q
Q
Q
H
Operation  
A
B
L
X
X
X
a … h  
a
b
h
Asynchronous Parallel Load  
H
H
L
L
L
H
X
X
L
H
Q
Q
Q
Q
An  
An  
Gn  
Gn  
Serial Shift via Clock  
H
H
L
L
L
H
X
X
L
H
Q
Q
Q
Q
An  
An  
Gn  
Gn  
Serial Shift via Clock Inhibit  
H
H
X
H
H
X
X
X
X
X
No Change  
No Change  
Inhibited Clock  
No Clock  
H
L
L
X
X
X = don’t care  
Q
– Q  
= Data shifted from the preceding stage  
Gn  
An  
10/95  
REV 6  
Motorola, Inc. 1995  
12345678

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与MC74HC165相关器件

型号 品牌 获取价格 描述 数据表
MC74HC165A ONSEMI

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 		8-Bit Serial or Parallel-Input/Serial-Output Shift Register
MC74HC165A MOTOROLA

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 		8-BIT SERIAL OR PARALLEL-INPUT/SERIAL-OUTPUT SHIFT REGISTER
MC74HC165A_05 ONSEMI

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 		8−Bit Serial or Parallel−Input/ Serial−Output Shift Register High−
MC74HC165A_16 ONSEMI

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 		8-Bit Serial or Parallel-Input/ Serial-Output Shift Register
MC74HC165AD ONSEMI

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 		8-Bit Serial or Parallel-Input/Serial-Output Shift Register
MC74HC165AD MOTOROLA

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 		8-Bit Serial or Parallel-Input/Serial-Output Shift Register
MC74HC165AD ROCHESTER

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 		HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDS
MC74HC165ADG ONSEMI

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 		8−Bit Serial or Parallel−Input/ Serial−Output Shift Register High−
MC74HC165ADR2 ONSEMI

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 		8-Bit Serial or Parallel-Input/Serial-Output Shift Register
MC74HC165ADR2G ONSEMI

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 		8−Bit Serial or Parallel−Input/ Serial−Output Shift Register High−

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