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MC74ACT109DTR2 PDF预览

MC74ACT109DTR2

更新时间: 2024-11-30 05:22:19
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 233K
描述
Dual JK Positive Edge−Triggered Flip−Flop

MC74ACT109DTR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP16,.25
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.73
系列:ACTJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:J-KBAR FLIP-FLOP
最大频率@ Nom-Sup:125000000 Hz最大I(ol):0.024 A
位数:2功能数量:2
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):235电源:5 V
传播延迟(tpd):13 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:125 MHz
Base Number Matches:1

MC74ACT109DTR2 数据手册

 浏览型号MC74ACT109DTR2的Datasheet PDF文件第2页浏览型号MC74ACT109DTR2的Datasheet PDF文件第3页浏览型号MC74ACT109DTR2的Datasheet PDF文件第4页浏览型号MC74ACT109DTR2的Datasheet PDF文件第5页浏览型号MC74ACT109DTR2的Datasheet PDF文件第6页浏览型号MC74ACT109DTR2的Datasheet PDF文件第7页 
MC74AC109, MC74ACT109  
Dual JK Positive  
Edge−Triggered Flip−Flop  
The MC74AC109/74ACT109 consists of two highspeed  
completely independent transition clocked JK flipflops. The clocking  
operation is independent of rise and fall times of the clock waveform.  
The JK design allows operation as a D flipflop (refer to  
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs  
together.  
http://onsemi.com  
Asynchronous Inputs:  
DIP16  
N SUFFIX  
CASE 648  
LOW input to S (Set) sets Q to HIGH level  
LOW input to C (Clear) sets Q to LOW level  
D
16  
D
Clear and Set are independent of clock  
1
Simultaneous LOW on C and S makes both Q and Q HIGH  
D
D
SO16  
D SUFFIX  
CASE 751B  
Outputs Source/Sink 24 mA  
ACT109 Has TTL Compatible Inputs  
16  
1
V
C
J
2
K
CP  
S
Q
Q
2
CC  
D2  
2
2
D2  
2
16  
15  
14  
13  
12  
11  
10  
9
TSSOP16  
DT SUFFIX  
CASE 948F  
C
J
K
CP  
S
D
Q
16  
D
Q
1
C
D1  
J
K
1
CP  
S
D1  
Q
Q
1
1
1
1
EIAJ16  
M SUFFIX  
CASE 966  
1
2
4
5
6
7
8
3
16  
C
J
1
K
CP  
S
Q
Q
GND  
D1  
1
1
D1  
1
1
1
Figure 1. Pinout; 16Lead Packages Conductors  
ORDERING INFORMATION  
(Top View)  
Device  
Package  
Shipping  
PIN ASSIGNMENT  
MC74AC109N  
MC74ACT109N  
MC74AC109D  
MC74ACT109D  
MC74AC109DR2  
25 Units/Rail  
25 Units/Rail  
48 Units/Rail  
48 Units/Rail  
PDIP16  
PDIP16  
SOIC16  
SOIC16  
PIN  
J , J , K , K  
2
FUNCTION  
Data Inputs  
1
2
1
CP , CP  
Clock Pulse Inputs  
Direct Clear Inputs  
Direct Set Inputs  
Outputs  
1
2
C , C  
D1 D2  
SOIC16 2500 Tape & Reel  
S
, S  
D1 D2  
MC74ACT109DR2  
MC74AC109DT  
2500 Tape & Reel  
96 Units/Rail  
SOIC16  
Q , Q , Q ,  
1
2
2
1
TSSOP16  
Q
MC74ACT109DT  
MC74AC109DTR2  
MC74ACT109DTR2  
MC74AC109M  
96 Units/Rail  
2500 Tape & Reel  
2500 Tape & Reel  
50 Units/Rail  
TSSOP16  
TSSOP16  
TSSOP16  
EIAJ16  
50 Units/Rail  
MC74ACT109M  
MC74AC109MEL  
MC74ACT109MEL  
EIAJ16  
2000 Tape & Reel  
2000 Tape & Reel  
EIAJ16  
EIAJ16  
DEVICE MARKING INFORMATION  
See general marking information in the device marking  
section on page 6 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 Rev. 6  
MC74AC109/D  

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