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MC74ACT109NC PDF预览

MC74ACT109NC

更新时间: 2024-11-06 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 201K
描述
ACT SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, DIP-16

MC74ACT109NC 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.4Is Samacsys:N
系列:ACTJESD-30 代码:R-PDIP-T16
长度:19.175 mm负载电容(CL):50 pF
逻辑集成电路类型:J-KBAR FLIP-FLOP位数:2
功能数量:2端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):11.5 ns
认证状态:Not Qualified座面最大高度:4.44 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:125 MHz
Base Number Matches:1

MC74ACT109NC 数据手册

 浏览型号MC74ACT109NC的Datasheet PDF文件第2页浏览型号MC74ACT109NC的Datasheet PDF文件第3页浏览型号MC74ACT109NC的Datasheet PDF文件第4页浏览型号MC74ACT109NC的Datasheet PDF文件第5页浏览型号MC74ACT109NC的Datasheet PDF文件第6页 
DUAL JK POSITIVE  
EDGE-TRIGGERED  
FLIP-FLOP  
The MC74AC109/74ACT109 consists of two high-speed completely independent  
transition clocked JK flip-flops. The clocking operation is independent of rise and fall  
times of the clock waveform. The JK design allows operation as a D flip-flop (refer to  
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.  
Asynchronous Inputs:  
LOW input to S (Set) sets Q to HIGH level  
D
LOW input to C (Clear) sets Q to LOW level  
D
Clear and Set are independent of clock  
Simultaneous LOW on C and S makes both Q and Q HIGH  
D
D
N SUFFIX  
CASE 648-08  
PLASTIC  
Outputs Source/Sink 24 mA  
• ′ACT109 Has TTL Compatible Inputs  
V
C
J
K
CP  
S
Q
Q
2
CC  
D2  
2
2
2
D2  
2
16  
15  
14  
13  
12  
11  
10  
9
C
D
J
K
CP  
S
D
Q
Q
D SUFFIX  
CASE 751B-05  
PLASTIC  
PIN NAMES  
C
D1  
1
J , J , K , K  
Data Inputs  
J
K
1
CP  
S
Q
1
Q
1
1
2
1
2
2
1
D1  
CP , CP  
Clock Pulse Inputs  
Direct Clear Inputs  
Direct Set Inputs  
Outputs  
1
C
S
, C  
, S  
D1 D2  
1
2
4
5
6
7
8
3
D1 D2  
Q , Q , Q , Q  
2
C
J
K
1
CP  
S
Q
Q
1
GND  
1
2
1
D1  
1
1
D1  
1
LOGIC SYMBOL  
TRUTH TABLE  
Inputs  
Outputs  
Q
J
Q
K
S
C
CP  
J
K
Q
Q
D
D
S
C
D
D
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
L
H
L
X
X
X
L
H
L
H
H
H
CP  
CP  
L
H
L
L
Toggle  
H
H
X
Q
Q -  
0
0
Q
J
Q
K
H
X
H
L
Q -  
0
S
C
D
D
L
Q
0
H = HIGH Voltage Level  
L = LOW Voltage Level  
= LOW-to-HIGH Clock Transition  
X = Immaterial  
Q (Q ) = Previous Q (Q ) before  
0
0
0
0
LOW-to-HIGH Transition of Clock  
FACT DATA  
5-1  

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