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MC74ACT112N PDF预览

MC74ACT112N

更新时间: 2024-11-29 23:01:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
6页 194K
描述
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

MC74ACT112N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
系列:ACTJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.175 mm
负载电容(CL):50 pF逻辑集成电路类型:J-K FLIP-FLOP
最大频率@ Nom-Sup:125000000 Hz最大I(ol):0.024 A
位数:2功能数量:2
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):14.5 ns
认证状态:Not Qualified座面最大高度:4.44 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:7.62 mm
最小 fmax:125 MHzBase Number Matches:1

MC74ACT112N 数据手册

 浏览型号MC74ACT112N的Datasheet PDF文件第2页浏览型号MC74ACT112N的Datasheet PDF文件第3页浏览型号MC74ACT112N的Datasheet PDF文件第4页浏览型号MC74ACT112N的Datasheet PDF文件第5页浏览型号MC74ACT112N的Datasheet PDF文件第6页 
DUAL JK NEGATIVE  
EDGE-TRIGGERED  
FLIP-FLOP  
The MC74AC112/74ACT112 consists of two high-speed completely independent  
transition clocked JK flip-flops. The clocking operation is independent of rise and fall  
times of the clock waveform. The JK design allows operation as a D flip-flop (refer to  
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.  
Asynchronous Inputs:  
LOW input to S (Set) sets Q to HIGH level  
D
LOW input to C (Clear) sets Q to LOW level  
D
Clear and Set are independent of clock  
Simultaneous LOW on C and S makes both Q and Q HIGH  
D
D
N SUFFIX  
CASE 648-08  
PLASTIC  
Outputs Source/Sink 24 mA  
• ′ACT112 Has TTL Compatible Inputs  
CONNECTION DIAGRAM  
V
C
C
CP  
K
J
S
Q
2
CC  
D1  
D2  
2
2
2
D2  
10  
16  
15  
14  
13  
12  
11  
9
D SUFFIX  
CASE 751B-05  
PLASTIC  
S
C
C
S
J
D
D Q  
Q
K
CP  
CP  
K
Q
Q
J
D
D
LOGIC SYMBOL  
1
2
3
J
4
5
6
7
8
CP  
K
1
S
Q
Q
1
Q
2
GND  
4
10  
1
1
D1  
1
MODE SELECT — TRUTH TABLE  
S
S
D
D
3
5
6
11  
9
J
Q
Q
J
Q
Q
Inputs  
Outputs  
Operating Mode  
S
C
J
K
Q
Q
1
2
13  
12  
D
D
CP  
K
CP  
K
Set  
L
H
L
L
H
H
H
H
X
X
X
h
l
X
X
X
h
h
l
H
L
H
q
L
H
H
q
7
Reset (Clear)  
*Undetermined  
Toggle  
Load “0” (Reset)  
Load “1” (Set)  
Hold  
H
L
H
H
H
H
C
C
D
D
L
H
q
H
L
q
15  
14  
V
= PIN 16  
CC  
h
l
GND = PIN 8  
l
*BothoutputswillbeHIGHwhilebothS andC areLOW,buttheoutputstates  
D
D
are unpredictable if S and C go HIGH simultaneously.  
H, h = HIGH Voltage Level  
D
D
L, l = LOW Voltage Level  
X = Don’t Care  
l, h (q) = Lower case letters indicate the state of the referenced input  
(or output) one set-up time prior to the HIGH to LOW clock transition.  
FACT DATA  
5-1  

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