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MC74AC175DTR2 PDF预览

MC74AC175DTR2

更新时间: 2024-10-31 14:30:43
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
12页 88K
描述
AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, TSSOP-16

MC74AC175DTR2 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.54系列:AC
JESD-30 代码:R-PDSO-G16长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:139000000 Hz最大I(ol):0.012 A
位数:4功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:3.3/5 V传播延迟(tpd):14.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:187 MHzBase Number Matches:1

MC74AC175DTR2 数据手册

 浏览型号MC74AC175DTR2的Datasheet PDF文件第2页浏览型号MC74AC175DTR2的Datasheet PDF文件第3页浏览型号MC74AC175DTR2的Datasheet PDF文件第4页浏览型号MC74AC175DTR2的Datasheet PDF文件第5页浏览型号MC74AC175DTR2的Datasheet PDF文件第6页浏览型号MC74AC175DTR2的Datasheet PDF文件第7页 
MC74AC175, MC74ACT175  
Quad D Flip-Flop With  
Master Reset  
The MC74AC/ACT175 is a high–speed quad D flip–flop. The  
device is useful for general flip–flop requirements where clock and  
clear inputs are common. The information on the D inputs is  
transferred to storage during the LOW–to–HIGH clock transition.  
The device has a Master Reset to simultaneously clear all flip–flops,  
when MR is low.  
http://onsemi.com  
The MC74AC/ACT175 consists of four edge–triggered D  
flip–flops with individual D inputs and Q and Q outputs. The Clock  
(CP) and Master Reset (MR) are common to all flip–flops. Each D  
input’s state is transferred to the corresponding flip–flop’s output  
following the LOW–to–HIGH Clock (CP) transition. A LOW input  
to the Master Reset (MR) will force all Q outputs LOW and Q  
outputs HIGH independent of Clock or Data inputs. The  
MC74AC/ACT175 is useful for applications where the Clock and  
Master Reset are common to all storage elements.  
DIP–16  
N SUFFIX  
CASE 648  
16  
1
SO–16  
D SUFFIX  
CASE 751B  
16  
1
Outputs Source/Sink 24 mA  
ACT175 Has TTL Compatible Inputs  
TSSOP–16  
DT SUFFIX  
CASE 948F  
16  
1
V
CC  
Q
3
Q
3
D
D
Q
Q
2
CP  
9
3
2
2
16  
15  
14  
13  
12  
11  
10  
EIAJ–16  
M SUFFIX  
CASE 966  
16  
1
1
2
3
4
5
6
7
8
ORDERING INFORMATION  
MR  
Q
0
Q
0
D
0
D
1
Q
1
Q
1
GND  
Device  
Package  
Shipping  
Figure 1. Pinout: 16–Lead Packages  
(Top View)  
MC74AC175N  
MC74ACT175N  
MC74AC175D  
MC74ACT175D  
MC74AC175DR2  
25 Units/Rail  
25 Units/Rail  
PDIP–16  
PDIP–16  
SOIC–16  
PIN ASSIGNMENT  
PIN  
– D  
FUNCTION  
Data Inputs  
Clock Pulse Input  
Master Reset Input  
Outputs  
48 Units/Rail  
D
0
3
48 Units/Rail  
SOIC–16  
SOIC–16  
CP  
2500 Tape & Reel  
MR  
MC74ACT175DR2  
MC74AC175DT  
2500 Tape & Reel  
96 Units/Rail  
SOIC–16  
Q
Q
– Q  
– Q  
0
0
3
TSSOP–16  
Outputs  
3
MC74ACT175DT  
MC74AC175DTR2  
MC74ACT175DTR2  
MC74AC175M  
96 Units/Rail  
2500 Tape & Reel  
2500 Tape & Reel  
50 Units/Rail  
TSSOP–16  
TSSOP–16  
TSSOP–16  
EIAJ–16  
DEVICE MARKING INFORMATION  
See general marking information in the device marking  
section on page 6 of this data sheet.  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
May, 2001 – Rev. 5  
MC74AC175/D  

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