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MC74AC194 PDF预览

MC74AC194

更新时间： 2024-11-23 05:10:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
7页 217K
描述
4-Bit Bidirectional Universal Shift Register

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MC74AC194 数据手册

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4-BIT BIDIRECTIONAL  
UNIVERSAL SHIFT  
REGISTER  
The MC74AC194/74ACT194 is a high-speed 4-bit bidirectional universal shift  
register. As a high-speed multifunctional, sequential building block, it is useful in  
a wide variety of applications. It may be used in serial-serial, shift left, shift right,  
serial-parallel, parallel-serial, and parallel-parallel data register transfers. The  
′AC/ACT194 is similar in operation to the ′AS195 universal shift register, with  
added features of shift left without external connections and hold (do nothing)  
modes of operation.  
• Typical Shift Frequency of 150 MHz  
• Asynchronous Master Reset  
• Hold (Do Nothing) Mode  
• Fully Synchronous Serial or Parallel Data Transfers  
N SUFFIX  
CASE 648-08  
PLASTIC  
FUNCTIONAL DESCRIPTION  
The MC74AC/74ACT194 contains four edge-triggered D flip-flops and the  
necessary interstage logic to synchronously perform shift right, shift left, parallel  
load and hold operations. Signals applied to the Select (S , S ) inputs  
0
1
determine the type of operation, as shown in the Mode Select Table. Signals  
on the Select, Parallel data (P –P ) and Serial data (D , D ) inputs can  
change when the clock is in either state, provided only that the recommended  
setup and hold times, with respect to the clock rising edge, are observed. A  
LOW signal on Master Reset (MR) overrides all other inputs and forces the  
outputs LOW.  
0
3
SR SL  
D SUFFIX  
CASE 751B-05  
PLASTIC  
MODE SELECT TABLE  
V
1
2
3
4
5
6
7
8
16  
15  
14  
13  
MR  
CC  
Inputs  
Outputs  
Operating  
Mode  
D
Q
SR  
0
1
MR  
L
S
S
D
D
P
Q
Q
Q
Q
1
0
SR  
X
SL  
n
0
1
2
3
Reset  
Hold  
X
X
X
X
X
L
L
L
L
P
Q
0
H
l
l
X
X
q
0
q
1
q
2
q
3
P
Q
1
2
H
H
h
h
l
l
X
X
l
X
X
q
1
q
1
q
2
q
2
q
3
q
3
L
Shift Left  
h
H
12  
11  
10  
9
P
Q
2
3
H
H
l
l
h
h
l
X
X
X
X
L
q
0
q
0
q
1
q
1
q
2
2
Shift Right  
h
H
q
P
CP  
3
Parallel Load  
H
h
h
X
X
p
p
0
p
1
p
2
p
3
n
S
1
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.  
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition.  
D
SL  
S
P
(q ) = Lower case letters indicate the state of the referenced input (or output) one setup  
0
n
n
GND  
time prior to the LOW-to-HIGH clock transition.  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
2
3
4
5
6
7
D
P
P
P
P D  
SR  
0
1
2 3 SL  
S
9
0
S
10  
11  
1
CP  
MR  
1
Q
Q
Q
Q
0
1
2 3  
15 14 13 12  
FACT DATA  
5-1  
1234567

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